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Charles J. Poirier

dblp:90/5612 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 92% Integrated circuit design · 8%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › cell layout
cell layout generation		 0.011989
Excellerator: custom CMOS leaf cell layout generator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation
physical design		 0.011989
Excellerator: custom CMOS leaf cell layout generator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation › physical design
routing		 0.011989
Excellerator: custom CMOS leaf cell layout generator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation › CAD framework
VLSI design environment		 0.011983
A vertically integrated VLSI design environment · DAC 1983

Methods — techniques the papers use, named apart from their topics

recursive routing · 0.0a-star search · 0.0
YearPublicationVenuePosition
1989 Excellerator: custom CMOS leaf cell layout generator
abstract
A description is given of a program, Excellerator, which automatically generates full-custom symbolic CMOS cell layouts. The input is a transistor-level netlist with optimal constraints on layout shape and I/O port positions. The output is a high-quality virtual-grid-based layout suitable for use in a two-dimensional tiling methodology. I/O port locations can be optimized. Versatile support for different layout shapes and port locations makes this system ideal for use in a top-down, fully automatic physical design system. Transistor routing is provided by a novel, recursive version of the A-Star search procedure. This technique reduces the frequency and seriousness of routing blockages by finding near-optimal compromises between new connections and reroutes of previous connections. Routing occurs in two metal layers plus polysilicon and diffusion, and is easily extendable to any number of routing layers. Routing priority can be given to critical nodes.>
Charles J. Poirier
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1983 A vertically integrated VLSI design environment
Jonathan B. Rosenberg, David G. Boyer, John A. Dallen, Stephen W. Daniel, Charles J. Poirier, John Poulton, C. Durward Rogers, Neil Weste
 DAC5