Many techniques for parallelizing a sequentially coded program have been developed and put to practical use, but there are many cases in which program codes cannot be parallelized because it is impossible to assure that their parallel execution does not violate the data dependencies in the program. To parallelize such programs, we have previously proposed speculative memory (SM). With SM, programmers can specify the parallel and speculative execution of threads explicitly in their programs. The SM system manages the memory data that are speculatively read or written by the threads running in parallel. When the system detects inconsistent memory accesses, it recovers the computational state of the program and restarts the execution. If such inconsistencies are not encountered often, we can expect the total execution time of the program to be shorter. In this paper we present a software implementation of SM (SSM). We have developed an SM library by using POSIX threads. In spite of large overheads that are essentially unavoidable in a software implementation, our SSM system can shorten the execution time of a program that compilers cannot parallelize automatically.

Transactional memory (TM) is promising to make parallel programming easier. Many hardware implementations of transactional memory (HTM) have been proposed to improve the performance, but they still suffer from some overheads when a transaction either commits or aborts. So we have been developing a novel new HTM design, called Delayed-Committing TM (DCTM), which enables transactions of arbitrary size to commit or abort in a fixed number of cycles - typically, one. In this paper, we analyze the performance of our DCTM system in detail. Simulation results show that the performance of our DCTM system is as much as 35.7% better than the performance of a conventional HTM system, which has almost no overhead when a transaction aborts but detects conflict and publishes speculatively modified data when a transaction commits. Furthermore, we can expect to improve performance more by increasing the bandwidth of the common bus connecting processing nodes with each other.

We have proposed a distributed storage system which dynamically makes storage tiers and optimizes location of data blocks autonomously. This aims to enhance the I/O performance of the storage system without remarkable network overhead. Our system dynamically organizes storage tiers considering device characteristics. And the data blocks will be placed in a suitable storage tier according to their access pattern. In this paper, we propose a method to select the destination storage node for migration using an access characteristic of a data block to be migrated. This method ranks the storage nodes dynamically, and each storage node configures storage tiers autonomously. Simulation results show that our scheme can short the execution time of a program with file I/O by 49% at maximum, in comparison with the static migration without considering the access characteristics of the migration data.

We have been developing a multiprocessor architecture which executes iterations of a loop speculatively in parallel. In this paper, we present speculative memory (SM), in order to enable the large-scale speculation which supports the speculative execution of the iteration of arbitrary size and duration. With SM, a programmer can hint explicitly that iterations of a certain loop are preferable to be executed speculatively in parallel. SM manages multiple values (versions) of speculatively modified data. SM also features the memory renaming and the delayed execution of the program codes, which could be viewed as a dynamic code migration. These can remove the dependencies between loop iterations or alleviate the occurrence of dependency hazards. Thus, SM can improve the success rate of the speculation, and consequently, makes it possible to extract the thread-level parallelism more than ever before.

In our previous work, we had proposed a distributed storage system which aims to optimize the locations of data blocks on the basis of their access frequency. In order to relocate data blocks at an appropriate node, each node should collect fresh information about storage utilization of other nodes. However, frequent information exchange might become the cause of network congestion. In this paper, we propose a method to improve the storage information freshness and to suppress information exchange traffic. This method controls the propagation interval according to the condition of a storage node. We also show that Ethernet frames can be reduced by merging packets even if storage information is transferred at short intervals.

We proposed a computer with low-level parallelism as one of the basic computer architectures and built a large scale experimental system called QA-2. By low-level parallelism, we mean that a long-word instruction controls simultaneously many ALUs, busses, registers and memories in a mode of fine-grained parallelism. The QA-2 employs a 256-bit instruction by which four different ALU operations, four memory accesses to different/continuous locations and one powerful sequence control are all specified and performed in parallel. If many simultaneously executable operations are detected and embedded in one instruction at compile time, this type of computer can provide a high-degree of performance for a wide variety of applications. This paper describes the architectural benefits and limitations of low-level parallelism in performing 3-D color image generation and interpreting Prolog/Lisp programs. The hardware organization with four ALUs, which are actually implemented in the QA-2, is verified to be adequate. In fact, nearly three out of four ALUs can work in parallel. Any architecture with more than four ALUs can not achieve a significant degree of performance enhancement. This paper also shows the degree of performance improvement achieved by the techniques such as ALU chaining and highly-structured sequence control mechanisms. As compared with the IBM 370 architecture, the QA-2 can generate 3-D color images in 1/5 of dynamic instruction steps. The compiler version of Prolog machine on the QA-2 is as fast (45K LIPS) as the ICOT's PSI. From all results, we expect that the QA-2 is a high-performance computer which will be utilized in the future personal computing environment.

This paper describes the architecture of a dynamically microprogrammable computer with low-level parallelism, called QA-2, which is designed as a high-performance, local host computer for laboratory use. The architectural principle of the QA-2 is the marriage of high-speed, parallel processing capability offered by four powerful Arithmetic and Logic Units (ALUs) with architectural flexibility provided by large scale, dynamic user-microprogramming. By changing its writable control storage dynamically, the QA-2 can be tailored to a wide spectrum of research-oriented applications covering high-level language processing and real-time processing.

A new microprogrammable computer with low-level parallelism was built and has been utilized as a research vehicle for solving different classes of research-oriented applications such as real-time processings on static/dynamic images, pictures and signals, and emulations of both existing and virtual machines including high (intermediate) level language machines. The design goal of the machine was to achieve a high degree of processing enhancement in research- oriented applications by means of a low-level parallel processing organization combined with dynamically microprogrammable control. The machine has the capability to process multiple data streams, performing parallel operations with four 16-bit ALU's. These ALU's are independently controlled by the different fields of a 160-bit horizontal-type microinstruction, and have simultaneous access to 15 working registers. This microprogrammed MIMD organization is expected to provide a greater degree of flexibility for low-level parallel processing. In addition, not only does the machine contain powerful ALU's and a large number of registers, but also it employs flexible control structures and a hierarchical organization of control storage. All of these combine to yield extensive microprogramming capability which the user can effectively tailor to a wide spectrum of applications.