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Vladimir Levin

dblp:90/604 · DBLP profile ↗
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20ranked-venue papers
2as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 16 · 2 first-authorTheory of computation · 10 · 2 first-authorSystems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
3 papers
Program analysis · 38% Program verification · 30% Operating systems · 30%
Theoretical computer science
4 papers
Automated reasoning and model checking · 88% Coding theory · 12%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 84% Embedded and real-time systems · 16%

Topics — the 12 heaviest of 15, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
hardware verification
0.222011
Formalizing hardware/software interface specifications · ASE 2011
Efficient Reachability Analysis of Büchi Pushdown Systems for Hardware/Software Co-verification · CAV 2010
Automated reasoning and model checking
model checking
0.132002
Compressing Transitions for Model Checking · CAV 2002
Model Checking for an Executable Subset of UML · ASE 2001
SDLcheck: A Model Checking Tool · CAV 2001
Program analysis
static analysis
0.122010
Thorough static analysis of device drivers · EuroSys 2006
The Static Driver Verifier Research Platform · CAV 2010
Program analysis › error detection
API usage error detection
0.112006
Thorough static analysis of device drivers · EuroSys 2006
Operating systems › i/o › i/o subsystem
device drivers
0.112006
Thorough static analysis of device drivers · EuroSys 2006
Operating systems › i/o › i/o subsystem › device drivers
device driver verification
0.112006
Thorough static analysis of device drivers · EuroSys 2006
Coding theory
source coding
0.012002
Compressing Transitions for Model Checking · CAV 2002
Automated reasoning and model checking › model checking
state space reduction
0.012002
Compressing Transitions for Model Checking · CAV 2002
Electronic design automation › hardware verification and test › functional verification › system-level verification
hardware/software co-verification
0.012010
Efficient Reachability Analysis of Büchi Pushdown Systems for Hardware/Software Co-verification · CAV 2010
Automated reasoning and model checking › model checking › software model checking
UML model checking
0.012001
Model Checking for an Executable Subset of UML · ASE 2001
Program verification
model checking
0.012006
Thorough static analysis of device drivers · EuroSys 2006
Requirements engineering and software design
model-driven engineering
0.012001
Model Checking for an Executable Subset of UML · ASE 2001

Methods — techniques the papers use, named apart from their topics

reachability analysis · 0.2relative atomicity · 0.1formal specification · 0.1static analysis engine · 0.1state space reduction · 0.1model transformation · 0.1API usage rules · 0.1transition compression · 0.0
YearPublicationVenuePosition
2020 Angelic Checking within Static Driver Verifier: Towards high-precision defects without (modeling) cost
abstract
Microsoft's Static Driver Verifier (SDV) pioneered the use of software model checking for ensuring that device drivers correctly use operating system (OS) APIs.However, the verification methodology has been difficult to extend in order to support either (a) new classes of drivers for which SDV does not already have a harness and stubs, or (b) memory-corruption properties.Any attempt to apply SDV out-of-the-box results in either false alarms due to the lack of environment modeling, or scalability issues when finding deeply nested bugs in the presence of a very large number of memory accesses.In this paper, we describe our experience designing and shipping a new class of checks known as angelic checks through SDV with the aid of angelic verification (AV) [1] technology, over a period of 4 years.AV pairs a precise inter-procedural assertion checker with automatic inference of likely specifications for the environment.AV helps compensate for the lack of environment modeling and regains scalability by making it possible to find deeply nested bugs, even for complex memorycorruption properties.These new rules have together found over a hundred confirmed defects during internal deployment at Microsoft, including several previously unknown high-impact potential security vulnerabilities.AV considerably increases the reach of SDV, both in terms of drivers as well as rules that it can support effectively.
Shuvendu K. Lahiri, Akash Lal, Sridhar Gopinath, Alexander Nutz, Vladimir Levin, Rahul Kumar 0002, Nate Deisinger, Jakob Lichtenberg, Chetan Bansal
FMCAD5
2011 Model Checking Büchi Pushdown Systems
Juncao Li, Thomas Ball 0001, Vladimir Levin
FASE4
2011 Formalizing hardware/software interface specifications
abstract
Software drivers are usually developed after hardware devices become available. This dependency can induce a long product cycle. Although co-simulation and co-verification techniques have been utilized to facilitate the driver development, Hardware/Software (HW/SW) interface models, as the test harnesses, are often challenging to specify. Such interface models should have formal semantics, be efficient for testing, and cover all HW/SW behaviors described by HW/SW interface protocols. We present an approach to formalizing HW/SW interface specifications, where we propose a semantic model, relative atomicity, to capture the concurrency model in HW/SW interfaces; demonstrate our approach via a realistic example; elaborate on how we have utilized this approach in device/driver development process; and discuss criteria for evaluating our formal specifications. We have detected fifteen issues in four English specifications. Furthermore, our formal specifications are readily useful as the test harnesses for co-verification, which has discovered twelve real bugs in five industrial driver programs.
Juncao Li, Thomas Ball 0001, Vladimir Levin, Con McGarvey
ASE4
2010 The Static Driver Verifier Research Platform
Thomas Ball 0001, Ella Bounimova, Vladimir Levin, Rahul Kumar 0002, Jakob Lichtenberg
CAV3
2010 Efficient Reachability Analysis of Büchi Pushdown Systems for Hardware/Software Co-verification
Juncao Li, Thomas Ball 0001, Vladimir Levin
CAV4
2010 An Automata-Theoretic Approach to Hardware/Software Co-verification
Juncao Li, Thomas Ball 0001, Vladimir Levin, Con McGarvey
FASE4
2010 SLAM2: Static driver verification with under 4% false alarms
Thomas Ball 0001, Ella Bounimova, Rahul Kumar 0002, Vladimir Levin
FMCAD4
2006 Thorough static analysis of device drivers
abstract
Bugs in kernel-level device drivers cause 85% of the system crashes in the Windows XP operating system [44]. One of the sources of these errors is the complexity of the Windows driver API itself: programmers must master a complex set of rules about how to use the driver API in order to create drivers that are good clients of the kernel. We have built a static analysis engine that finds API usage errors in C programs. The Static Driver Verifier tool (SDV) uses this engine to find kernel API usage errors in a driver. SDV includes models of the OS and the environment of the device driver, and over sixty API usage rules. SDV is intended to be used by driver developers "out of the box." Thus, it has stringent requirements: (1) complete automation with no input from the user; (2) a low rate of false errors. We discuss the techniques used in SDV to meet these requirements, and empirical results from running SDV on over one hundred Windows device drivers.
Thomas Ball 0001, Ella Bounimova, Byron Cook, Vladimir Levin, Jakob Lichtenberg, Con McGarvey, Bohus Ondrusek, Sriram K. Rajamani, Abdullah Ustuner
EuroSys4
2004 Translating Software Designs for Model Checking
Vladimir Levin, Robert P. Kurshan, James C. Browne
FASE2
2004 SLAM and Static Driver Verifier: Technology Transfer of Formal Methods inside Microsoft
Thomas Ball 0001, Byron Cook, Vladimir Levin, Sriram K. Rajamani
IFM3
2004 Static driver verifier, a formal verification tool for Windows device drivers
abstract
Microsoft is improving the quality of system software, in particular, through the intensive application of formal methods. The ultimate goal is to reach a point at which robustness against failures and attacks can be guaranteed. To support this goal, the company has invested in advanced testing and verification tools. Examples include model-based testing supported by AsmL/SpeC#, TLC and Zing model checkers for concurrency verification, a type system augmented with pre-/post- conditions (Fugue), advanced static analysis tools (PreFix, ESP, etc.) and Static Driver Verifier, SDV. SDV is a formal verification tool aimed at checking device drivers developed using the Windows Driver Model (WDM) interface. The WDM interface consists of more than 800 functions - entry points into the kernel functionality. To correctly use the WDM interface is not easy: WDM rules are numerous and complicated.
Vladimir Levin
MEMOCODE1
2004 Automatic Creation of Environment Models via Training
Thomas Ball 0001, Vladimir Levin
TACAS2
2004 Lessons Learned from Model Checking a NASA Robot Controller
Natasha Sharygina, James C. Browne, Robert P. Kurshan, Vladimir Levin
Formal Methods Syst. Des.5
2002 Compressing Transitions for Model Checking
Robert P. Kurshan, Vladimir Levin, Hüsnü Yenigün
CAV2
2002 ObjectCheck: A Model Checking Tool for Executable Object-Oriented Software System Designs
Vladimir Levin, James C. Browne
FASE2
2002 Combining Software and Hardware Verification Techniques
Robert P. Kurshan, Vladimir Levin, Marius Minea, Doron A. Peled, Hüsnü Yenigün
Formal Methods Syst. Des.2
2001 SDLcheck: A Model Checking Tool
Vladimir Levin, Hüsnü Yenigün
CAV1
2001 Model Checking for an Executable Subset of UML
abstract
The paper presents an approach to model checking software system designs specified in xUML (http://www.kc.com/html/xuml.html), an executable subset of UML. This approach is enabled by the execution semantics of xUML and is based on automatic translation from xUML to S/R, the input language of the COSPAN model checker (R.H. Hardin et al., 1996). Model transformations are applied to reduce the state space of the resulting S/R model that is to be verified by COSPAN. An xUML level logic for specifying properties to be checked is defined. Automated support is provided for translating properties specified in the logic to S/R representations and mapping error traces generated by COSPAN to xUML representations.
Vladimir Levin, James C. Browne
ASE2
1998 Static Partial Order Reduction
Robert P. Kurshan, Vladimir Levin, Marius Minea, Doron A. Peled, Hüsnü Yenigün
TACAS2
1997 Verifying hardware in its software context
Robert P. Kurshan, Vladimir Levin, Marius Minea, Doron A. Peled, Hüsnü Yenigün
ICCAD2