Vinoo Srinivasan

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5ranked-venue papers

3as first author

0since 2021 · last 1999

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 3 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 70% Reconfigurable computing and FPGAs · 23% Performance modeling and evaluation · 7%

Topics — the 4 heaviest of 5, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation › physical design circuit partitioning	1	1999	Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures · FPGA 1999
Electronic design automation design space exploration	1	1999	Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures · FPGA 1999
Reconfigurable computing and FPGAs › multi-FPGA system multi-FPGA architecture	1	1999	Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures · FPGA 1999
Electronic design automation physical design	1	1999	Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures · FPGA 1999

Methods — techniques the papers use, named apart from their topics

design space exploration · 0.0

Year	Publication	Venue	Position
1999	Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures abstract This paper presents SPADE, a system for partitioning designs onto multi-FPGA architectures. The input to SPADE is a task graph, that is composed of computational tasks, memory tasks and the communication and synchronization between tasks. SPADE consist of an iterative partitioning engine, an architectural constraint evaluator, and a throughput optimization and RTL design space exploration heuristic. We show how various architectural constraints can be effectively handled using an iterative partitioning engine. Vinoo Srinivasan, Ranga Vemuri	FCCM	1
1999	Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures abstract No abstract available. Vinoo Srinivasan, Ranga Vemuri	FPGA	1
1998	Hardware Software Partitioning with Integrated Hardware Design Space Exploration abstract This paper presents an integrated approach to hardware software partitioning and hardware design space exploration. We propose a genetic algorithm which performs hardware software partitioning on a task graph while simultaneously contemplating various design alternatives for tasks mapped to hardware. We primarily deal with data dominated designs typically found in digital signal processing and image processing applications. A detailed description of various genetic operators is presented. We provide results to illustrate the effectiveness of our integrated methodology. Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri	DATE	1
1998	An Effective Design System for Dynamically Reconfigurable Architectures abstract The SPARCS system is an integrated partitioning and synthesis environment for reconfigurable architectures. In this paper, we use the Joint Photographic Experts Group (JPEG) image compression algorithm as a design example to demonstrate the effectiveness of dynamic reconfiguration achieved using SPARCS. We present a typical design process using the SPARCS system consisting of temporal partitioning, spatial partitioning, and design synthesis. The results, obtained on a commercial RC architecture, show that the multiply-reconfigured version of the JPEG compression algorithm achieves reasonable improvement in execution times compared to the one-time configured version. Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri	FCCM	4
1996	Rapid Prototyping of Reconfigurable Coprocessors abstract We describe the process of hardware-software codesign of a JPEG-like still image compression system. The hardware components are targeted to execute on a reconfigurable hardware coprocessor which communicates with a host computer that executes all the software tasks. Central to our codesign methodology is the usage of software profiling, high-level estimation and synthesis tools. We describe the process of trade-off analysis and hardware task selection in detail. We present detailed experimental results gathered throughout the codesign process. Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri	ASAP	2