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Haksu Kim

dblp:90/6665 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2000
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design
clock routing		 0.012000
Efficient implementation of a planar clock routing with thetreatment of obstacles · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000
Electronic design automation › physical design › routing
obstacle avoidance		 0.012000
Efficient implementation of a planar clock routing with thetreatment of obstacles · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000
Electronic design automation
physical design		 0.012000
Efficient implementation of a planar clock routing with thetreatment of obstacles · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000
Electronic design automation › physical design
routing		 0.012000
Efficient implementation of a planar clock routing with thetreatment of obstacles · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000

Methods — techniques the papers use, named apart from their topics

planar obstacle-avoiding routing · 0.0cutting-line embedding · 0.0
YearPublicationVenuePosition
2000 Efficient implementation of a planar clock routing with thetreatment of obstacles
abstract
This paper presents a set of techniques for developing a planar clock routing with the treatment of obstacles in high speed VLSI design. The planar clock routing framework has two key components. The first component employs a cutting-line embedding (CLE) routine algorithm to construct a planar clock tree topology. The routing constructed by CLE contains crossings over the obstacles in the presence of obstacles. Thus, the second component is a planar obstacle-avoiding (POA) routing scheme to clean up those crossings. These two schemes together give a good enhancement in convenient usage and performance to build a planar clock routing.
Haksu Kim, Dian Zhou
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1