Phase-Locked Loops (PLLs) are versatile modules for synchronization and applications such as high-speed serial interfaces in System-on-Chips (SoCs). Their precisions are critical to proper functioning of the SoCs. Intermodule interference such as simultaneous switching noise (SSN) is time-varying, where the stationary assumption in conventional jitter analysis does not apply. We propose a methodology to compute PLL jitter by investigating the harmonic relations between the PLL system with SSN. This provides statistical analysis over many VCO design parameters, SoC modules and noise barrier configurations. Its accuracy and efficiency are compared against circuit simulations.

In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interference in mixed-signal environments cause designers to be less reliant on optimization based solely on schematic models. Performance can be further improved at the physical design level. Hierarchical optimization schemes are used to manage the complexity in the analog circuit design process. In this paper, we present a novel performance-driven compaction optimization algorithm that optimizes the placement of circuit blocks and guard bands for analog circuits. Parasitic effects are minimized under symmetry, matching and displacement constraints derived from the customized layout topology.