Large language models (LLMs) often show poor performance in low-resource languages like Korean, partly due to unique linguistic challenges such as homophonous Sino-Korean words that are indistinguishable in Hangul script. To address this semantic ambiguity, we propose HanjaBridge, a novel meaning-injection technique integrated into a continual pre-training (CPT) framework. Instead of deterministically mapping a word to a single Hanja (Chinese character), HanjaBridge presents the model with all possible Hanja candidates for a given homograph, encouraging the model to learn contextual disambiguation. This process is paired with token-level knowledge distillation to prevent catastrophic forgetting. Experimental results show that HanjaBridge significantly improves Korean language understanding, achieving a 21% relative improvement on the KoBALT benchmark. Notably, by reinforcing semantic alignment between Korean and Chinese through shared Hanja, we observe a strong positive cross-lingual transfer. Furthermore, these gains persist even when Hanja augmentation is omitted at inference time, ensuring practical efficiency with no additional run-time cost.

A 12.5-Gb/s 1/5-rate reference-less subsampling clock and data recovery (CDR) circuit is presented. The subsampling phase detection technique widely used in the low jitter phase-locked loop design is adopted for the CDR’s clock recovery operation. It brings not only a design simplification but also the low-power consumption of the CDR. The 1/5-rate subsampling phase detection circuit is also introduced for further power reduction. The false-lock detector is proposed that monotonically ascends or descends the clock frequency until the phase lock is achieved. It shares the outputs of the subsampling phase detection circuit and removes the frequency detector from the CDR loop. The measured power consumption and efficiency of the proposed CDR at 12.5 Gb/s are 8.8 mW and 0.7 pJ/bit, respectively. At the same time, the peak-to-peak and rms jitters show 21 and 3.7 ps in 2.5-GHz clock signal, respectively. The high-frequency jitter tolerance is 0.52 UIpp. The CDR including a 1-to-5 DEMUX occupies a core area of 0.087 mm2 using 65-nm CMOS process.

Orthogonal frequency division multiplexing (OFDM) has been thoroughly investigated as an enabling technology for future broadband multimedia communication. In this paper, we suggest adaptive bit allocation algorithms that operate in a frequency selective fading channel environment by exploiting channel state information obtained through a feedback channel. The proposed algorithms try to maximize the overall throughput of the system with significantly reduced complexity while guaranteeing that mean bit error rate (BER) of all sub-channels remains below the pre-defined BER threshold. To do that, the first proposed algorithm divides all sub-channels into several groups according to their signal-to-noise ratio (SNR). The grouping criteria are adaptive to the current channel state and BER constraint. The second algorithm tries to find the appropriate constellation size for each sub-channel. The proposed algorithms were compared with existing algorithms through simulation. The simulation results show that the proposed algorithms are close to optimum solution with significantly lower complexity.