The effective use of simulation for logic verification and test evaluation frequently requires simulation capabilities at different levels of detail. This paper discusses the functional level simulation capability in the LAMP system at Bell Laboratories and its relation to gate level simulation. The Function Definition Language (FDL) used for specifying the behavior of functional blocks is discussed. Functions described in this language can be embedded in gate level circuits and simulated to determine the normal circuit behavior or faulty behavior. Classical faults external to functions and user specified internal faults in functions may be simulated. The effectiveness of functional simulation has been demonstrated in a number of applications such as memory modules in a large controller of an Electronic Switching System, the ROM in a small controller and an entire microprocessor treated as an interconnection of a few functional blocks.