In modern software development, maintaining consistency between architectural documentation and implementation remains a significant challenge. This research explores how large language models (LLMs) can be integrated into an encoder-decoder framework to enable real-time architectural documentation and seamless conversion between semi-formal models (e.g., UML diagrams) and natural language descriptions. Building on previous work in LLM-based requirements verification, we develop a system that automatically converts models into text and vice versa. By allowing LLMs to assess textual descriptions for compliance with requirements, this approach reduces the need for extensive model-side validation through rule-based queries. Additionally, the decoder helps transform text-based process descriptions into structured architectural models, supporting digitalization in organizations. The system’s effectiveness is evaluated by comparing reconstructed models with their originals, assessing how well information is preserved and how accurately the transformations are performed.

ILLOD is a tool for detecting abbreviation-expansion pairs (AEPs) in requirement sets. It utilizes syntactic features such as Initial Letters, term Lengths, Order, and Distribution of characters to determine if a term is a potential long form to a given abbreviation. The artifact bundles all source code and data resources to replicate evaluation results presented for ILLOD in two research papers published at the REFSQ2022 Conference and in the Information and Software Technology (IST) journal. In addition, ILLOD can be used to detect AEPs, perform abbreviation detection, and the input data-set can be used for further research in requirements engineering or other related fields. The repository is organized into different directories containing data, Python sources, and notebooks for experiments and evaluations. Detailed instructions are provided to load and use the tool on a local system, and the results generated by ILLOD are stored in output files. The tool demonstrates its effectiveness in detecting AEPs and consolidating glossary terms, and the evaluation results provide insights into the performance of different classifiers. The artifact repository is a valuable resource for researchers and practitioners in the field of requirements engineering and related areas.

Summary We introduce a new model for the task mapping problem to aid in the systematic design of algorithms for heterogeneous systems including, but not limited to, CPUs, GPUs, and FPGAs. A special focus is set on the communication between the devices, its influence on parallel execution, as well as on device‐specific differences regarding parallelizability and streamability. We give a comprehensive description on how a given task mapping can be abstractly evaluated including mappings to dataflow‐based hardware accelerators. We show how this model can be utilized in different system design phases and present two novel mixed‐integer linear programs to demonstrate the usage of the model, showing significant improvements compared to pure CPU mapping for randomly generated task graphs. To the best of our knowledge, we present the first ILP for task mapping that considers pipelining effects when streaming tasks on an FPGA.