Article Free Access Share on Increasing design quality and engineering productivity through design reuse Authors: Emil Girczyc View Profile , Steve Carlson View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 48–53https://doi.org/10.1145/157485.164565Published:01 July 1993Publication History 56citation737DownloadsMetricsTotal Citations56Total Downloads737Last 12 Months38Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A generalized interconnect model for data path synthesis is presented. This is a multi-level interconnect model designed for synthesis under interconnect constraints. Two novel algorithms for dynamic interconnect allocation and interconnect synthesis are also described. These algorithms help implement the generalized interconnect model in the Elf hardware compiler.

STEM (SmallTalk Environment of Module design) is an IC design environment written in Smalltalk aimed at integrating design automation tools with manual design. STEM is based on the Smalltalk model-view-controller concept. Each cell in the database is represented by a single Smalltalk class. This serves as the “model” and encapsulates all (permanent) information about the cell. Different design representations of the single model are achieved by calculating views which are strictly temporary. All views of an object are linked to the model. This allows views to be updated whenever a change in the model's state is detected, and prevents permanent aliases of data. Design changes are entered using a Smalltalk controller attached to the model.

A novel approach to automatic data path synthesis is presented. This approach features innovations in the synthesis process as well as in the system implementation.

The requirements of an algorithmic level hardware description language can be met by a software language with only limited feature enhancement. This paper discusses the feasibility of using a subset of Ada as a hardware description language. Methods are presented for realizing the extra features required for hardware description within the syntax of Ada. This allows the compiled Ada program to act as a functional simulator. Our particular context for hardware description is as a source language for a hardware compiler. Rules are presented for translating a circuit described in the Ada subset onto a control/data-flow graph (CDFG), our intermediate level form.