In spite of significant advances in the development of low-power designs and power management techniques, power remains and will remain a first-class design constraint for mobile devices. The functionality integrated into mobile devices will only continue to grow with the increasing transition from PCs to super-phones. Power remains one of the critical hurdles to this transition, and without continued innovations in power management, the term "mobile" devices will be rendered moot. In addition to (and closely related to) power challenges in mobile devices are thermal challenges. Increasingly complex and rich functionality in mobile devices leads to higher power dissipation, and consequently, higher temperatures. However, thermal constraints are constant across successive device generations. Thermal limits, even more than power, will become the fundamental bottleneck to increasing the capabilities of such devices, making thermal management techniques crucial. This paper discusses some of the major challenges in power management and thermal management for current and next-generation mobile devices from a semiconductor industry perspective. Specifically, this paper discusses challenges in three areas: process-variability-aware power management, thermally aware power management and thermal management for mobile devices. Broadcom mobile chipsets feature multiple such advanced power and thermal management techniques, with active on-going research and development in each of these areas.

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture that can efficiently adapt thelogicalconnectivityof the communication architecture and the components connected to it. Flexbus achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through newdynamicbridgeby-pass, andcomponentremappingtechniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of Flexbus-based architectures.The techniques underlying Flexbus are general, and are applicable to a variety of bus standards. We have implemented Flexbus as an extension of the popular AMBA AHB bus, and have evaluated it using a commercial design flow. We report on experiments conducted to analyze its area, timing, and performance under a wide variety of system-level traffic profiles. We have applied Flexbus to two example SoC designs: 1) an IEEE 802.11 MAC processor and 2) an UMTS turbo decoder. Our results show that Flexbus provides gains of up to 34.55 % in application data-rates over conventional architectures, with negligible area overhead and a 3.2% penalty in clock period.

Dynamic variations in application functionality and performance requirements can lead to the imposition of widely disparate requirements on system-on-chip (SoC) platform hardware over time. This has led to interest in the design and use of adaptive SoC platforms that are capable of providing high performance in the face of such variations. Recent advances in circuits and architectures are enabling platforms that contain various mechanisms for runtime adaptation. However, the problem of exploiting such configurability in a coordinated manner at the system level remains a challenging task. In this work, we focus on two configurable subsystems of SoC platforms that play a crucial role in determining overall system performance, namely, the on-chip communication architecture, and the on-chip memory architecture. Using detailed case studies, we demonstrate the limitations of designs in which the architectural configuration of a bus-based communication architecture and the placement of data in memory are statically optimized, and those in which each is customized separately, without considering their interdependence. We propose an integrated methodology for dynamically relocating on-chip data and reconfiguring the communication architecture, and discuss the necessary hardware support. Experiments conducted on an SoC platform that integrates decoders for the UMTS (3G) and IEEE 802.11a (wireless LAN) standards demonstrate that the proposed integrated adaptation technique helps boost the maximum achievable performance by up to 32% over the best statically optimized design

In this paper, we describe FLEXBUS, a flexible, high-performance onchip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run-time variations in communication traffic characteristics, and efficiently adapt the topology of the communication architecture, both at the system-level, through dynamic bridge by-pass, as well as at the component-level, using component re-mapping. We describe the FLEXBUS architecture in detail and present techniques for its run-time configuration based on the characteristics of the on-chip communication traffic. The techniques underlying FLEXBUS can be used in the context of a variety of on-chip communication architectures. In particular, we demonstrate its application to AMBA AHB, a popular commercial on-chip bus. Detailed experiments conducted on the FLEXBUS architecture using a commercial design flow, and its application to an IEEE 802.11 MAC processor design, demonstrate that it can provide significant performance gains as compared to conventional architectures (up to 31.5% in our experiments), with negligible hardware overhead.

SUMMARY: A graphics package has been developed to display all side chain conformation angles of the user selected residue in a given protein structure. The proposed package is incorporated with all the protein structures (solved using X-ray diffraction and NMR spectroscopy) available in the Protein Data Bank. The package displays the multiple conformations adopted by a single amino acid residue whose structure is solved and refined at very high resolution. In addition, it shows the percentage distribution of the side chain conformation angles in different rotameric states. AVAILABILITY: http://144.16.71.146/cap/

For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods are based on either (i) inserting dedicated interconnect selftest structures (leading to significant area overhead), or (ii) using existing logic BIST structures (e.g., LFSRs), which often result in poor defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concerti. In this paper we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing LFSR structures but generates high-quality tests for interconnect crosstalk defects, while minimizing area overhead and interconnect power consumption. On applying LI-BIST to a DSP chip, we achieved crosstalk defect coverage of 99.7% for the interconnects and single stuck-at-fault coverage of 91.36% for the logic cores, while incurring an area overhead of only 4% over conventional logic BIST.

Abstract Summary: A graphics package has been developed to display the main chain torsion angles phi, psi (φ, Ψ); (Ramachandran angles) in a protein of known structure. In addition, the package calculates the Ramachandran angles at the central residue in the stretch of three amino acids having specified the flanking residue types. The package displays the Ramachandran angles along with a detailed analysis output. This software is incorporated with all the protein structures available in the Protein Databank. Availability: This package is available over the world wide web at http://144.16.71.146/rp/ or http://dicsoft1.physics.iisc.ernet.in/rp. Contact: [email protected] * To whom correspondence should be addressed. † This work is dedicated to Late Professor G. N. Ramachandran.

At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test methodologies, which can be used by processors to test themselves at-speed. Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. In this paper, we report our experiences in applying a commercial BIST methodology to two processor cores and analyze the problems associated with the current hardware-based BIST methodologies. We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets, and the test application program applies the tests to the components-under-test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.