This work addresses congestion attacks on prioritization and preemption signal applications (PPSA), an important variant of cooperative intelligent transport systems (C-ITS). In PPSA, priority vehicles, such as buses and ambulances, can request traffic signal adjustments in their favor to reduce travel time. These systems rely on vehicle-to-everything (V2X) communications, which makes them vulnerable to congestion attacks. When under attack, these systems experience disruptions in information exchange between vehicles and infrastructure, leading to traffic congestion and safety hazards. Nevertheless, existing solutions do not address the attacks at a system level and within the PPSA context. Our proposal presents a software framework designed to enhance both sustainability and safety during congestion attacks. Specifically, it introduces a whitelist-based traffic-filtering mechanism that preserves system sustainability by ensuring only legitimate priority requests are processed. Additionally, a monitoring mechanism evaluates the PPSA service rate at runtime to identify and address potential safety risks arising from insufficient service rates. Moreover, we analyze the limitations of a machine learning-based defense method and highlight risks of potential service unavailability due to false positives. We believe that this research contributes to the development of a secure and safe traffic management system for smart cities.

Data deduplication enhances storage efficiency through non-destructive compression but is often hindered by the chunking process, which requires scanning the entire dataset. While traditional methods leveraging conventional architectures and hardware accelerators (e.g., GPUs and FPGAs) have been developed to address this issue, they continue to face challenges related to excessive data movement and associated performance degradation. These limitations stem from the von Neumann architecture, where computation and storage are separated in a processor-centric design, necessitating multiple memory hierarchy traversals and causing inefficiencies. To overcome these challenges, we explore UPMEM’s DPU, a processing-in-memory (PIM) technology that reduces data movement by performing computations directly within memory. However, designing a deduplication system for DPUs presents unique obstacles, including restricted inter-DPU data sharing, the absence of native multiplication support, and significant DPU-CPU communication overhead. In response, we propose PIMDup, a DPU-optimized deduplication system that addresses these constraints through efficient parallelization, DPU-friendly chunking techniques, and reduced data transfer volumes. Experimental results demonstrate that PIMDup improves chunking performance without compromising deduplication accuracy, achieving a $1.67 \times$ speedup over CPU-based systems while maintaining 100% result consistency.

Emerging resistive random access memory (RRAM) attracts considerable interest in computing-in-memory by its high efficiency in multiply-accumulate operation, which is the key computation in the neural network (NN). However, due to the imperfect fabrication, RRAM cells suffer from the variations, which make the values in RRAM cells deviate from the target values so that the accuracy of the RRAM-based NN accelerator degrades significantly. Moreover, in a practical hardware design of RRAM-based NN accelerators, if the number of wordlines and bitlines in a crossbar array activated at the same time increases, ADCs with a high resolution are required and the power consumption of ADC increases. This paper proposes a novel methodology to mitigate the impact of variations in RRAM-based neural network accelerators. The methodology includes a unary-based non-uniform quantization method and a variation-aware operation unit (OU) based framework. The unary-based non-uniform quantization method equalizes the significance of weights stored in each RRAM cell to reduce the impact of variations. The variation-aware OU-based framework activates only RRAM cells in the same OU at the same time, which reduces the power consumption of ADCs. Additionally, the framework introduces three methods, including OU skipping, OU recombination, and OU compensation, to further mitigate the impact of variations. The experiments show that the proposed approach outperforms the state-of-the-art among four NN models on two datasets with 2-bit cell resolution.

Recent researches have proposed multi-tiered storage systems that extend the storage hierarchy by using solid-state drives (SSDs) to cache data from the hard disk drives (HDDs). However, the current Linux readahead architecture fails to fully support the multi-tiered storage systems. To address this issue, we propose a new Linux readahead architecture. To make prefetching decisions, the framework analyzes not only the degree of data access sequentiality, but also the performance model of the destined storage device and the access regularities of the I/O workload on the corresponding storage device.

As cloud computing and big data applications become more popular, the demand for large capacity memory and data preservation in memory increases. Therefore, nonvolatile memory (NVM) with high capacity is being actively developed. A hybrid memory that comprises both NVM and DRAM and provides both high access speed and nonvolatility has become a major trend. However, compared to DRAM, NVM in the hybrid memory typically suffers from a shorter lifetime and higher latency. To improve the lifetime and address the latency issues associated with hybrid memory, we propose a global clean page first replacement (GCPF) to reduce the write operations to NVM. We also propose an index-aware multistream prefetcher (IAMSP) that considers the indexes of prefetch candidates individually so as to prefetch pages from NVM more accurately. Benchmarks with a large memory footprint are used to evaluate the proposed schemes. The experimental results show that GCPF enhances lifetime by 56.8% as compared to LRU, on average. When applying prefetching schemes on GCPF, the lifetime is insignificantly degraded. In addition, IAMSP reduces DRAM misses by 42.0% as compared to LRU, while a modern prefetcher that can change the prefetch degree dynamically only reduces DRAM misses by 38.0%, on average. When applying both GCPF and IAMSP, the average access latency can be reduced by 28.8% as compared to LRU.

Emerging non-volatile memories (NVMs) have favorable properties, such as low leakage and high density, and have attracted a lot of attention in recent years. Among them, spin-transfer torque magnetoresistive random access memory (STT-MRAM) with SRAM-comparable read speed is a good candidate to build large last-level caches (LLCs). However, STT-MRAM suffers from long write latency and high write energy. To mitigate the impact of asymmetric read/write energy and latency, hybrid cache designs have been proposed to combine the merits of STT-MRAM and SRAM. In such a hybrid SRAM/STT-MRAM LLC, intelligent block placement and migration policies are needed to improve the energy efficiency. Prior studies map write-intensive blocks to SRAM and keep read-intensive blocks in STT-MRAM for reducing the energy consumption of hybrid LLCs. The write-intensive/read-intensive blocks are usually captured by sampling the address (PC) of memory access instructions or adding simple access counters in each cache line. Nevertheless, these prior approaches cannot fully capture the energy-harmful access behavior in STT-MRAM, especially the writes caused by repetitive data transfer between the LLC and upper-level caches. In this paper, we find that conflict misses in L2 often generate thrashing blocks which move back and forth between L2 and LLC. If dirty thrashing blocks that incur extensive writes are placed in STT-MRAM, energy consumption would excessively increase, especially when running memory-bound workloads. Thus, we propose a thrashing aware placement and migration policy (TAP) to tackle the challenge. TAP places dirty thrashing blocks into SRAM and migrates clean thrashing blocks from SRAM to STT-MRAM. Evaluation results show that TAP can provide significant energy savings with minimal performance loss.

Scratchpad memory (SPM), a software-controlled on-chip memory, is being increasingly used in embedded systems to reduce on-chip memory energy consumption. To further reduce energy consumption, multibank SPM architecture is proposed. In multibank SPM, each bank can be accessed independently, and unused banks can enter the low power mode, thus reducing leakage energy. However, if both frequently and infrequently used data exist in the same bank, the bank will not be able to enter the low power mode, resulting in less energy reduction. To address this issue, we propose online page clustering for multibank SPM (OCMAS) to reduce the leakage energy in multibank SPM. OCMAS groups SPM pages with similar access frequencies into the same bank, allowing banks containing infrequently used data to stay in low power mode longer. We also propose a method to dynamically adjust the thresholds for determining cold pages (pages that contain infrequently used data), so banks that contain cold pages can enter the low power mode with a shorter idle timeout. Compared to conventional timeout-based, periodic drowsy, and bank-based methods, OCMAS can reduce the energy delay product by up to 37.67% (18.14% on average), 39.53% (22.38% on average), and 132.32% (23.34% on average) in 32 KB 4-bank SPM, by up to 25.33% (15.71% on average), 29.87% (15.92% on average), and 72.25% (22.64% on average) in 32 KB 8-bank SPM, by up to 28.99% (13.45% on average), 30.71% (14.74% on average), and 96.67% (19.94% on average) in 16 KB 4-bank SPM, and by up to 30.18% (10.05% on average), 32.13% (11.62% on average), and 65.56% (16.2% on average) in 16 KB 8-bank SPM. The area overhead is approximately 0.72%, which is insignificant.

With the widespread use of cloud computing and the Internet, applications that require a large memory footprint, such as in-memory databases, have gained in popularity. These applications depend on a high capacity, reliable memory architecture. To achieve these two goals, hybrid memory that uses both DRAM and nonvolatile memory (NVM) provides benefits that include large capacity and nonvolatility. However, NVM is usually accompanied by high write latency and endurance problems. It is important to reduce NVM writes and improve the latency and lifetime of hybrid memory. One way to reduce NVM writes is to reduce dead pages that occupy DRAM and have not been accessed for a long time. When dead pages are removed from the memory, more space can be reserved for frequently accessed data, reducing DRAM misses and NVM writes. Currently, there are several dead block prediction techniques that can identify dead blocks and reduce miss rates at the cache level. However, they are not effective at the memory level because CPU memory accesses exhibit less locality when accesses are filtered by caches. To propose an application that is suitable at the memory level and to achieve a reduction in NVM writes, this paper proposes a simple but effective dead page predictor, called the infection-based dead page predictor (IDP), for the memory level. IDP uses the access counts of evicted pages to determine if nearby pages are also dead pages (i.e., other pages are infected by evicted pages). The simulation results show that compared to related work, the proposed predictor significantly reduces DRAM misses and enhances lifetime.

In a multi-tiered storage system, both page cache and solid-state drives are used as the cache of hard disk drives. However, in the current I/O architecture, page cache and SSD cache are managed independently. Thus, page cache and SSD cache managers make the caching and replacement decisions independently. As a result, system performance is limited due to factors including metadata duplication and improper management of the page cache and SSD cache spaces. To address the limitations of the current I/O architecture, we propose a new I/O architecture to enable the information sharing between the page cache and SSD cache managers. By our proposed architecture, the page cache and SSD cache managers can cooperate with each other so that the overall I/O performance is maximized.

Many studies have shown that energy consumption of on-chip memory is a critical issue for multicore embedded systems. In order to reduce energy consumption, scratchpad memory (SPM), a software controlled on-chip memory, has been increasingly used. In a typical multicore embedded system that uses SPM in the on-chip memory, each core has local SPM and can access data in both local SPM and SPMs of other cores (i.e., remote SPM). Since the latency and energy of accessing remote SPMs is higher than accessing local SPM, how data are allocated in local and remote SPMs influences the performance and energy consumption of the system. This paper proposes a requirement-aware online hybrid on-chip memory management (ROHOM) method. This method contains an SPM supervisor that determines the SPM allocation of each task according to the dynamic access behavior and SPM requirements of the task. In addition, two policies: 1) free remote SPM space first and 2) get local SPM space first, are proposed in ROHOM to reduce the access frequency of remote SPMs. The experimental results show ROHOM can reduce energy delay product up to 69% (42% on average) in an 8-core system and up to 69% (50% on average) in a 16-core system when compared to a contention aware SPM allocation method. The hardware area overhead is insignificant (about 1.8%).

A hybrid file system with high flexibility and performance, called Trident file system (TridentFS), is proposed to manage three types of storage with different performance characteristics, that is, Non-Volatile RAM (NVRAM), flash memory and magnetic disk. Unlike previous NVRAM-based hybrid file systems, novel techniques are used in TridentFS to improve the flexibility and performance. TridentFS is flexible by the support of various forms of flash memory and a wide range of NVRAM size. The former is achieved on the basis of the concept of stackable file systems, and the latter is achieved by allowing data eviction from the NVRAM. TridentFS achieves high performance by keeping hot data in the NVRAM and allowing data evicted from the NVRAM to be parallel distributed to the flash memory and disk. A data eviction policy is proposed to determine the data to be evicted from the NVRAM. Moreover, a data distribution algorithm is proposed to effectively leverage the parallelism between flash memory and disk during data distribution. TridentFS is implemented as a loadable module on Linux 2.6.29. The performance results show that it works well for both small-sized and large-sized NVRAM, and the proposed eviction policy outperforms LRU by 27%. Moreover, by effectively leveraging the parallelism between flash memory and disk, the proposed data distribution algorithm outperforms the RAID-0 and a size-based distribution method by up to 471.6% and 82.6%, respectively. By considering the data size and performance characteristics of the storage, the proposed data distribution algorithm outperforms the greedy algorithm by up to 15.5%. Copyright © 2014 John Wiley & Sons, Ltd.

The NAND flash memory has been widely used in computer and consumer electronic devices. A multilevel-cell (MLC) NAND flash memory allows two or more bits to be stored per cell, improving the cell density and, hence, reducing the cost. The lower price of the MLC NAND has made it appearing in both consumer product and datacenter markets. In MLC NAND, the page read latency varies according to the page type. For read-dominated workloads, placing read-intensive data into pages with longer read latencies may result in degraded read performance. In this brief, an online method called FastRead is proposed to improve the read performance of MLC NAND-based storage. The FastRead method dynamically identifies read-intensive data and migrates them to pages with shorter read latency to improve the read performance. According to the performance results, FastRead can reduce the read response time by up to 22% (17% on average) for read-dominated workloads on a Triple-level cell NAND. In addition, FastRead does not have noticeable performance impact for write-dominated workloads, and the overhead is insignificant.

Recently, a hybrid disk drive that integrates a small amount of flash memory within a mechanical drive has received significant attention. The hybrid drive extends the storage hierarchy by using flash memory to cache data from the mechanical disk. Unfortunately, current caching architectures fail to fully exploit the potential of the hybrid drive. Furthermore, current disk input/output (I/O) schedulers are optimized for rotational mechanical disk drives and thus must be re-targeted for the hybrid disk drive. In this paper, we propose a new data caching scheme, called Profit Caching, for hybrid drives. Profit Caching is a self-optimizing caching algorithm. It considers and seamlessly integrates all possible data characteristics that impact the performance of hybrid drives, including read count, write count, sequentiality, randomness, and recency, to determine the caching policy. Moreover, we propose a hybrid disk-aware Completely Fair Queuing (HA-CFQ) scheduler to avoid unnecessary I/O anticipations of the CFQ scheduler. We have implemented Profit Caching and HA-CFQ scheduler in the Linux kernel. Coupled with a trace-driven simulator, we have also conducted detailed experiments under a variety of workloads. Experimental results show that Profit Caching provides significantly improved performance compared with the previous schemes. In particular, the throughput of Profit Caching outperforms previous Random Access First and FlashCache caching schemes by factors of up to 1.8 and 7.6, respectively. In addition, the HA-CFQ scheduler reduces the total execution time of the CFQ scheduler by up to 1.74%. Finally, the experimental results show that the runtime overhead of Profit Caching is extremely insignificant and can be ignored. Copyright © 2014 John Wiley & Sons, Ltd.

Performance isolation is critical in shared storage systems, a popular storage solution. In a shared storage system, interference between requests from different users can affect the accuracy of I/O cost accounting, resulting in poor performance isolation. Recently, NAND flash-memory-based solid-state drives (SSDs) have been increasingly used in shared storage systems. However, interference in SSD-based shared storage systems has not been addressed. In this article, two types of interference, namely, queuing delay (QD) interference and garbage collection (GC) interference, are identified in a shared SSD. Additionally, a framework called VSSD is proposed to address these types of interference. VSSD is composed of two components: the FACO credit-based I/O scheduler designed to address QD interference and the ViSA flash translation layer designed to address GC interference. The VSSD framework aims to be implemented in the firmware running on an SSD controller. With VSSD, interference in an SSD can be eliminated and performance isolation can be ensured. Both synthetic and application workloads are used to evaluate the effectiveness of the proposed VSSD framework. The performance results show the following. First, QD and GC interference exists and can result in poor performance isolation between users on SSD-based shared storage systems. Second, VSSD is effective in eliminating the interference and achieving performance isolation between users. Third, the overhead of VSSD is insignificant.

Scratchpad memory (SPM) has been increasingly used in embedded systems due to its higher efficiency in terms of energy and area compared to that of ordinary cache. A hybrid on-chip memory architecture that combines SPM with a mini-cache has been proposed. One key issue for hybrid on-chip memory architectures is to reduce the number of off-chip memory accesses and energy consumption. Existing methods achieve this by moving the most frequently accessed data into SPM. However, these methods may be ineffective because the main source of off-chip memory accesses may not be the most frequently accessed data. Instead, most off-chip memory accesses are caused by cache misses, so reducing the latter will reduce the former. Cache misses are mainly caused by data contending for cache lines. Therefore, this paper proposes a contention-aware SPM allocation method for hybrid on-chip management. The number of cache misses for a page is used as a metric to determine whether a page should be moved to SPM. When the number of misses for a page exceeds a threshold, the page is moved to SPM, reducing cache contention. Experimental results show that the proposed method can reduce the energy delay product by 35% to 53% compared to a cache-only on-chip memory architecture and 19% to 31% compared to an existing hybrid on-chip memory architecture.

Increasing the degree of parallelism and reducing the overhead of garbage collection (GC overhead) are the two keys to enhancing the performance of solid-state drives (SSDs). SSDs employ multichannel architectures, and a data placement scheme in an SSD determines how the data are striped to the channels. Without considering the data access pattern, existing fixed and device-level data placement schemes may have either high GC overhead or poor I/O parallelism, resulting in degraded performance. In this article, an adaptive block-level data placement scheme called BLAS is proposed to maximize the I/O parallelism while simultaneously minimizing the GC overhead. In contrast to existing device-level schemes, BLAS allows different data placement policies for blocks with different access patterns. Pages in read-intensive blocks are scattered over various channels to maximize the degree of read parallelism, while pages in each of the remaining blocks are attempted to be gathered in the same physical block to minimize the GC overhead. Moreover, BLAS allows the placement policy for a logical block to be changed dynamically according to the access pattern changes of that block. Finally, a parallelism-aware write buffer management approach is adopted in BLAS to maximize the degree of write parallelism. Performance results show that BLAS yields a significant improvement in the SSD response time when compared to existing device-level schemes. In particular, BLAS outperforms device-level page striping and device-level block striping by factors of up to 8.75 and 7.41, respectively. Moreover, BLAS achieves low GC overhead and is effective in adapting to workload changes.

A Flash Translation Layer (FTL) determines the physical location of each written page on a NAND flash storage. Hot/cold data separation prevents placing data with different degrees of hotness together and is critical for an FTL to improve its performance. In existing FTLs, separation of hot and cold data was achieved by exploiting either temporal or spatial locality of the workloads. The both types of localities were not considered at the same time. In addition, in FTLs that consider the spatial locality, the storage is divided into fixedsize partitions, whose size cannot be adapted according to the workloads. Measurement results show that, a single fixed partition size cannot fit all the workloads, and the preferred partition size for a given workload may not be fixed all the time during the execution of the workload.In this paper, an FTL called DuLASP (Dual Localities with Adaptive Space Partitioning) is proposed. DuLASP considers both temporal and spatial localities of the workloads to achieve hot/cold data separation. Moreover, it incorporates a proposed technique called adaptive space partitioning (ASP) to adaptively and dynamically adjust the partition size according to the executed workloads. ASP achieves the goal by periodically evaluating the suitableness of partition size configuration and adjusting the partition size. Evaluation of the suitableness of a partition size is done mainly based on the temporal information of the data access, and the adjustment of the partition size is performed by merging neighboring partitions (i.e., increasing partition size) or splitting partitions (i.e., decreasing partition size).Experimental results on 7 realistic or benchmark-based workloads show that considering both types of localities has performance improvement (in terms of cleaning cost) of up to 16.8 times (3.1 times in average), compared to that considering only a single type of locality. Moreover, adaptive space partitioning also has significant performance improvement (i.e., by up to 92%, 23.8% in average), compared to the best fixed partitioning.

SUMMARY Journaling file systems, which are widely used in modern operating systems, guarantee file system consistency and data integrity by logging file system updates to a journal, which is a reserved space on the storage, before the updates are written to the data storage. Such journal writes increase the write traffic to the storage and thus degrade the file system performance, especially in full data journaling, which logs both metadata and data updates. In this paper, a new journaling approach is proposed to eliminate journal writes in server virtualization environments, which are gaining in popularity in server platforms. Based on reliable hardware subsystems and virtual machine monitor (VMM), the proposed approach eliminates journal writes by retaining journal data (i.e. logged file system updates) in the memory of each virtual machine and ensuring the integrity of these journal data through cooperation between the journaling file systems and the VMM. We implement the proposed approach in Linux ext3 in the Xen virtualization environment. According to the performance results, a performance improvement of up to 50.9journaling approach of ext3 due to journal write elimination. In metadata‐write dominated workloads, this approach could even outperform the metadata journaling approaches of ext3, which do not guarantee data integrity. These results demonstrate that, on virtual servers with reliable VMM and hardware subsystems, the proposed approach is an effective alternative to traditional journaling approaches. Copyright © 2011 John Wiley & Sons, Ltd.

Many consumer embedded system products nowadays are built on platforms with System-On-a-Chip (SOC) in which two or more processor cores, which are not necessarily of the same type, are put into a single chip and form the architecture of Chip-level Multi-Processor (CMP). Although such platform is capable of achieving high performance at relatively low cost, the system architecture of CMP brings new challenges in system development and increases complexity in developing embedded software especially at the level of kernel or operating system. This paper presents our experience and some preliminary results from building a multi-kernel embedded system with high performance Inter-Process Communication (IPC) mechanism for application software running on the platform of a newly developed multi-core SOC, namely PAC Duo SOC, which is the latest product from the PAC (short for Parallel Architecture Core) Project implemented at Industry Technology Research Institute (ITRI) in Taiwan. PAC Duo SOC is a heterogeneous multi-processor SOC composed of one ARM926 core serving as the general purpose processor (GPP) and two ITRI PAC DSP cores serving as the special purpose processors (SPP). We ported Linux operating system to run on the ARM926 processor and ported the real-time kernel Micro-C/OS-II to run on one PAC DSP core, leaving the other PAC DSP core with the option of running either another Micro-C/OS-II or a different kernel. To address the issues in IPC, a high performance message-passing mechanism is developed. Its design not only takes application-specific requirements into account but also takes advantages of hardware features.

Virtualization is becoming widely deployed in commercial servers. In our previous study, we proposed Virtual Machine Aware journaling (VMA journaling), a file system journaling approach for virtual server environments. With reliable VMM and hardware subsystems, VMA journaling eliminates journal writes while ensuring file system consistency and data integrity in virtual server environments, allowing it to be an effective alternative to traditional journaling approaches in these environments. In recent years, solid-state disks (SSDs) have shown their potential as a replacement of traditional magnetic disks in commercial servers. In this paper, we demonstrate the benefits of VMA journaling on SSDs. We compare the performance of VMA journaling and three traditional journaling approaches (i.e., the three journaling modes of the ext3 journaling file system) in terms of lifetime and garbage collection overhead, which are two key performance metrics for SSDs. Since a Flash Translation Layer (FTL) is used in an SSD to emulate traditional disk interface and the SSD performance highly depends on the FTL being used, three state-of-the-art FTLs (i.e., FAST, Super Block FTL and DFTL) are implemented for performance evaluation. The performance results show that, traditional full data journaling could reduce the lifetime of the SSD significantly. VMA journaling extends the SSD lifetime under full data journaling by up to 86.5%. Moreover, GC overhead is reduced by up to 80.6% when compared to the full data journaling approach of ext3. Finally, VMA journaling is effective under all the FTLs. These results demonstrate that VMA journaling is effective in SSD-based virtual server environments.

A Flash Translation Layer (FTL) provides a block device interface on top of flash memory to support disk-based file systems. Due to the erase-before-write feature of flash memory, an FTL usually performs out-of-place updates and uses a cleaning procedure to reclaim stale data. A hybrid address translation (HAT)-based FTL combines coarse-grained and fine-grained address translation to achieve good performance while keeping the size of the mapping information small. In this paper, we propose a new HAT-based FTL, called ROSE, which includes three novel techniques for reducing the cleaning cost. First, it reduces high-cost reclamation by preventing data in an entire-block sequential write from being placed into multiple physical blocks while eliminating the cleaning cost resulting from mispredicting random or semisequential writes as sequential ones. Second, it uses a merge-aware cleaning policy that considers both the block age and the merge cost in a HAT-based FTL for improving the cleaning efficiency. Third, it delays the erasure of obsolete blocks and reuses their free pages for buffering more writes. Simulation results show that the proposed FTL outperforms existing HAT-based FTLs in terms of both cleaning cost and flash write time by up to 47 times and 1.6 times, respectively.

Abstract Software is critical for Internet service availability since an Internet service may become unavailable due to software faults or software maintenance. In this paper, we propose a framework to allow zero‐loss recovery and online maintenance for Internet services. The framework is based on the virtual machine (VM) technology and a connection migration technique called FT‐TCP. It can recover transient application/operating system faults and it allows fault recovery and online maintenance on a single host. The framework substantially enhances FT‐TCP so that it can be run efficiently in the VM environment. Specifically, we propose techniques to reduce the inter‐VM switches and communication. Moreover, we propose service‐specific optimizations to reduce the recovery time of FT‐TCP. Finally, the framework provides an interface for the service designers to implement more service‐specific optimizations. The framework was implemented by modifying an open source VM monitor, Xen, and the Linux kernel running on top of Xen. The effectiveness and efficiency of the framework were evaluated by running two Internet services, WWW proxy and FTP, on the proposed framework and measuring the impact on their performance. According to the experimental results, our approach causes only slight performance overhead (i.e. less than 4%) and memory overhead (i.e. less than 750 KB) for both the services. Copyright © 2007 John Wiley & Sons, Ltd.

Abstract Owing to long serving time and huge numbers of clients, Internet services can easily suffer from transient faults. Although restarting a service can solve this problem, information of the on‐line requests will be lost owing to the service restart, which is unacceptable for many commercial or transaction‐based services. In this paper, we propose an approach to achieve the goal of zero‐loss restart for Internet services. Under this approach, a kernel subsystem is responsible for detecting the transient faults, retaining the I/O channels of the service, and managing the service restart flow. In addition, some straightforward modifications to the service should be made to take advantage of the kernel support. To demonstrate the feasibility of our approach, we implemented the subsystem in the Linux kernel. Moreover, we modified a Web server and a CGI program to take advantage of the kernel support. According to the experimental results, our approach incurs little runtime overhead (i.e. less than 3.2%). When the service crashes, it can be restarted quickly (i.e. within 210 μs) with no information loss. Furthermore, the performance impact due to the service crash is small. These results show that the approach can efficiently achieve the goal of zero‐loss restart for Internet services. Copyright © 2006 John Wiley & Sons, Ltd.

As network-enabled embedded devices and Java grow in their popularity, embedded system researchers start seeking ways to make these devices Java-enabled. However, it is a challenge to apply Java technology to these devices due to their shortage of resources. In this paper, we propose EJVM (Economic Java Virtual Machine), an economic way to run Java programs on network-enabled and resource-limited embedded devices. Espousing the architecture proposed by distributed JVM, we store all Java codes on the server to reduce the storage needs of the client devices. In addition, we use two novel techniques to reduce the client-side memory footprints: server-side class representation conversion and on-demand bytecode loading. Finally, we maintain client-side caches and provide performance evaluation on different caching policies. We implement EJVM by modifying a freely available JVM implementation, Kaffe. From the experiment results, we show that EJVM can reduce Java heap requirements by about 20–50% and achieve 90% of the original performance. Copyright © 2001 John Wiley & Sons, Ltd.