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VLDB 2026 Research / reviewers in the wild / expert

Thomas A. Horvath

dblp:91/4576 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms › neuromorphic computing
brain-inspired computing		 0.212016
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications · SC 2016
Emerging computing paradigms
neuromorphic computing		 0.212016
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications · SC 2016
Emerging computing paradigms
neuromorphic hardware		 0.212016
Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications · SC 2016

Methods — techniques the papers use, named apart from their topics

software ecosystem · 0.2scalable systems · 0.2
YearPublicationVenuePosition
2016 Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications
abstract
Abstract not provided
Jun Sawada, Filipp Akopyan, Andrew S. Cassidy, Brian Taba, Michael DeBole, Pallab Datta, Rodrigo Alvarez-Icaza, Arnon Amir, John V. Arthur, Alexander Andreopoulos, Rathinakumar Appuswamy, Heinz Baier, Davis Barch, David J. Berg, Carmelo di Nolfo, Steven K. Esser, Myron Flickner, Thomas A. Horvath, Bryan L. Jackson, Jeffrey A. Kusnitz, Scott Lekuch, Michael Mastro, Timothy Melano, Paul Merolla, Steven E. Millman, Tapan K. Nayak, Norm Pass, Hartmut Penner, William P. Risk, Kai Schleupen, Ben Shaw 0001, Hayley Wu, Brian Giera, Adam Moody, T. Nathan Mundhenk, Brian Van Essen, Eric X. Wang, David P. Widemann, William E. Murphy, Jamie K. Infantolino, James A. Ross, Dale R. Shires, Manuel M. Vindiola, Raju Namburu, Dharmendra S. Modha
 SC18
1995 A Novel Memory Architecture to Achieve Minimal Rounding/Truncation Errors for N Dimensional Image Transformation
abstract
This paper describes a novel memory architecture to minimize truncation error for implementing N-Dimension decomposable transformation using consecutive one dimension (1D) transformation approach. The memory architecture utilizes the effective bit representation not only achieving minimal truncation error with a constrained memory size, but also minimizing memory size to fulfill a given accuracy requirement. A 8/spl times/8 2-D IDCT macro that used the proposed architecture is implemented. The cell count for the macro is 43 K cells and occupies 6 mm/sup 2/ using 0.5 /spl mu/m CMOS VLSI technology.
Min-Hsiung Lin, Gee-gwo Mei, Thomas A. Horvath, Robert J. Yagley, Roger S. Rutter
 ISCAS3