Biological wastewater treatment depends on complex microbial ecosystems. Microscopic analysis of activated sludge is a proven method for assessing treatment performance, relying on the identification and quantification of key microorganisms. Automating this process using object detection models like YOLOv11 can save time and improve consistency. However, training such models requires large annotated datasets, which is still a major limitation in niche areas.To overcome this, we generate synthetic images of tardigrades using the "Cut-Paste" method with various blending techniques. A core challenge lies in the synthetic-to-reality gap, which often limits the effectiveness of artificial data. We address this by testing four blending methods and a multi-blending technique, measuring their impact using mAP, Fréchet Inception Distance (FID) and CLIP Maximum Mean Discrepancy (CMMD). While mAP reflects detection accuracy, FID and CMMD quantify the distributional differences between synthetic and real images. Results show that multi-blending improves mAP by +0.27 and significantly reduces both FID and CMMD, demonstrating that high-quality synthetic data can effectively bridge the domain gap and boost microorganism detection in real-world wastewater monitoring.

Word-Level Decision Diagrams (WLDDs), like *BMDs or K*BMDs, have been introduced to overcome the limitations of Binary Decision Diagrams (BDDs), which are the state-of-the-art data structure to represent and manipulate Boolean functions. However, the size of these graph types largely depends on the variable ordering, i.e. it may vary from linear to exponential. In the meantime, dynamic approaches to find a good variable ordering are also known for WLDDs. In this paper we show how these approaches can be accelerated significantly using a combination of a lower bound computation and synthesis operations. In the experiments it turned out that by this technique, the runtime for dynamic minimization can be reduced by more than 40% on average without loss of quality.

Formal verification has become one of the most important steps in circuit design. In this context the verification of high-level Hardware Description Languages (HDLs), like VHDL, becomes increasingly important. In this paper we present a complete set of datapath operations that can be formally verified based on Word-Level Decision Diagrams (WLDDs). Our techniques allow a direct translation of HDL constructs to WLDDs. We present new algorithms for WLDDs for modulo operation and division. These operations turn our to be the core of our efficient verification procedure. Furthermore, we prove upper bounds on the representation size of WLDDs guaranteeing effectiveness of the algorithms. Our verification tool is totally automatic and experimental results are given to demonstrate the efficiency of our approach.

Multiplicative Binary Moment Diagrams (*BMDs) have recently been introduced as a data structure for verification. Using *BMDs it was for the first time possible to verify multiplier circuits with up to 256 bits. In this paper we use a modification of *BMDs, called positive *BMDs (p*BMDs), that allows to apply dynamic variable ordering, that is the most promising minimization technique for decision diagrams, to *BMDs. Furthermore, we study *BMDs representing Boolean functions. We show that in this case for some operations polynomial algorithms can be given, while the general case of integer-valued functions requires exponential effort. Experimental results demonstrate that p*BMDs clearly outperform *BMDs with respect to runtime during dynamic minimization, while keeping (nearly) all advantages.

Word-Level Decision Diagrams (WLDDs), like *BMDs and K*BMDs, have recently been introduced as a data structure for verification. The size of WLDDs largely depends on the chosen variable ordering, i.e. the ordering in which variables are encountered, and on the decompositions carried out in each node. In this paper we present a framework for dynamic minimization of WLDDs. We discuss the difficulties with previous techniques if applied to WLDDs and present a new approach that efficiently adapts both variable ordering and decomposition type choice. Experimental results demonstrate that this method outperforms "classical" reordering with respect to runtime and representation size during dynamic minimization of word-level functions.

The problem of the optimization of complex data-paths relative to a repertoire of specified operations is discussed.Data-paths can be simplified if interconnections are functionally redundant.Redundancy is detected by means of the universal quantification of ROBDD representations of the data-path and of the specified operations.The full logical complexity of ALU's described at the gate-level is considered.A O-1 ILP formulation of the minimization problem is given and solved by means of ROBDD 's.A solution of the prelogic rectification problem for control-signals is present ed.