James R. Mann

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3ranked-venue papers

2as first author

0since 2021 · last 1988

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-authorArtificial intelligence and machine learning · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Hardware accelerators and domain-specific architectures · 67% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Integrated circuit design analog and mixed-signal circuits	1	1988	An Analog Self-Organizing Neural Network Chip · NIPS 1988
Hardware accelerators and domain-specific architectures › analog computing accelerator analog neural network	1	1988	An Analog Self-Organizing Neural Network Chip · NIPS 1988
Hardware accelerators and domain-specific architectures neural network hardware	1	1988	An Analog Self-Organizing Neural Network Chip · NIPS 1988

Methods — techniques the papers use, named apart from their topics

self-organizing map · 0.0

Year	Publication	Venue	Position
1988	An Analog Self-Organizing Neural Network Chip James R. Mann, Sheldon Gilbert	NIPS	1
1986	A wafer scale DTW multiprocessor James R. Mann, F. Matthew Rhodes	ICASSP	1
1984	A wafer scale integration systolic processor for connected word recognition abstract Current state-of-the-art speech recognition systems are based on dynamic time warping (DTW) techniques in which the dominant computational task is input/reference word template matching and input/reference word non-linear time registration. A systolic array wafer scale architecture is presented which exploits the parallelism and local interconnect properties of this computation. The array executes either isolated or connected word recognition using either LPC or spectrally based templates. Restructurable VLSI (RVLSI) technology is being used to implement such an array comprised of 65 bit-serial arithmetic processing elements on a monolithic silicon 3" wafer. Speech recognition systems based on the RVLSI circuits are projected to be capable of supporting real-time vocabularies as large as 12,000 words. Joel A. Feldman, Steven L. Garverick, F. Matthew Rhodes, James R. Mann	ICASSP	4