An efficient algorithm for analyzing a subset of transistor-level bridging faults is proposed. The complex analogue behavior of gate-to-drain shorts is handled using a network primitive into which the fault injected transistor is mapped. The resistances of the surrounding subnetworks obtained from a linear switch-level model are used together with a simple iteration scheme to predict the voltage at the shortened nodes. Fault simulation experiments were conducted and the algorithm shows good agreement with electrical-level analysis.

Transistor gate stuck-at and node stuck-at faults in self-testing checkers of various implementations are examined. Two types of CMOS implementations with different transistor driving strength ratios are considered. The coverage obtained for the classic gate-level stuck-at fault model for different test set sizes is compared with the corresponding coverage of transistor-level faults. It is shown that the coverage estimation using the gate-level stuck-at model is overly optimistic.

Two new switch-level algorithms with efficient management of unknown values are evaluated with respect to their fault modeling capability. The degradation of confidence in fault detection measures owing to unknown (X) output values is discussed and a strategy to quantify this uncertainty is proposed. It is demonstrated that this uncertainty can be decreased significantly when the node model is extended to include two resistances.

Abstract- An algorithm is presented for event-driven switch-level simulation of CMOS networks in which intermediate signal values are common. The proposed method is based on a local signal propagation scheme and an extended node model including both a logical low and a high contribution to the state of a node. The quantization effects of typical CMOS networks can thereby be modeled and, hence, the spread of undetermined logic values is in many cases prohibited. I.

The presence of realistic faults in CMOS networks, such as shorts and opens, frequently gives rise to intermediate voltage values. At the switch level, these values result in undetermined logic states which are likely to propagate to the outputs, causing an overly optimistic coverage estimation of test efficiency. A new method is presented that is efficient and well-suited for modeling switch-level networks when undetermined states are common. The concept of state dominance, introduced in this paper, is an improvement upon the well-known principle of dominance. The state dominance defines a dynamic direction of signal flow between neighboring nodes of undetermined logic state. A signal transformation scheme is proposed which solves bidirectional conflicts that may occur between adjacent nodes of undermined logic state without any network recomputation. The new concept is easily applicable to switch-level algorithms in which there is a distributed approach.

Several realistic transistor fault models were applied to circuit-level simulation models of code checkers in order to investigate the run-time fault testing capability. Various implementations of checkers designed for the detection of stuck-at faults were examined. A coverage varying from 99% to 100% was obtained for transistor terminal short faults and from 40% to 85% for open faults. A minimum set of four fault models for simulation-based evaluation of the self-testing property is proposed.

Two fault injection techniques for experimental validation of fault handling mechanisms in computer systems are investigated and compared. One technique is based on irradiation of ICs with heavy-ion radiation from a 252Cf source. The other technique uses voltage sags injected in the power supply rails to ICs. Both techniques have been used for fault injection experiments with the MC6809E microprocessor. Most errors generated by the 252Cf method were seen first in the address bus, while the power supply disturbances most frequently affected the control signals. An error classification shows that both methods generate many control flow errors, while pure data errors are infrequent. Results from a simulation experiment show that that the low number data errors in the 252Cf experiments can be explained by the fact that many errors in data registers are overwritten owing to the normal program execution.