A logic network is modeled with logic elements and a set of junctions formed by the interconnection of logic element pins. Electrical models for logic element pins are developed that include appropriate current and voltage parameters, and a consistent set of nomenclature for these parameters is introduced. An algorithm is then presented that can be used to determine the ability of ap element pin to force its junction to one or both of its valid logic states. The junctions may include bidirectional logic elements and wired-high and wired-low configurations. The algorithm evaluates every junction in the network and produces both error (fatal failure) and warning (possible failure) messages for each junction. This can be viewed as a "loading check" on the network. The noise margin for each junction is also computed and compared to a preselected value. Examples of the application of this algorithm on practical TTL circuits are presented.

A central issue in the design of multiprocessor systems is the interconnection network which provides communication paths between the processors. For large systems, high bandwidth interconnection networks will require numerous "network chips" with each chip implementing some subnetwork of the original larger network. Modularity and growth are important properties for such networks since multiprocessor systems may vary in size. This paper is concerned with the question of timing control of such networks. Two approaches, asynchronous and clocked, are used in the design of a basic network switching module. The modules and the approaches are then modeled and equations for network time delay are developed. These equations form the basis for a comparison between the two approaches. The importance of clock distribution strategies and clock skew is quantified, and a network clock distribution scheme which guarantees equal length clock paths is presented.

A central issue in the design of multiprocessor systems is the interconnection network which provides communications paths between the processors. For large systems, high bandwidth interconnection networks will require numerous 'network chips' with each chip implementing some subnetwork of the original larger network. Modularity and growth are important properties for such networks since multiprocessor systems may vary in size. This paper is concerned with the question of timing control of such networks. Two approaches, asynchronous and clocked, are used in the design of a basic network switching module. The modules and the approaches are then modelled and equations for network time delay are developed. These equations form the basis for a comparison between the two approaches. The importance of clock distribution strategies and clock skew is quantified, and a network clock distribution scheme which guarantees equal length clock paths is presented.

Multiple processor interconnection networks can be characterized as having N' inputs and N' outputs, each being B' bits wide. A major implementation constraint of large networks in the VLSI environment is the number of pins available on a chip, Np. Construction of large networks requires partitioning of the N' * N' * B' network into a collection of N * N switch modules with each input and output port being B (B ≤ B') bits wide. If each module corresponds to a single chip, then a large network can be implemented by interconnecting the chips in a particular manner. This correspondence presents a methodology for selecting the optimum values of N and B given values of N', B', Np, and the number of control lines per port. Models for both banyan and crossbar networks are developed and arrangements yielding minimum: 1) number of chips, 2) average delay through the network, and 3) product of number of chips and delay, are presented.

The interaction problem between asynchronous logic elements is formulated with emphasis on the synchronizer. A detailed analytic treatment of the binary flip-flop action in the metastable region is presented. The principle result is to predict, in a probabilistic manner, the time necessary to move from the metastable point to one of the stable boundaries. The effects of circuit time constant and circuit noise are discussed in detail. Theoretical results are correlated with laboratory measurements and suggestions for acceptable probability of error performance are given.

This paper describes the teaching of computer design using a new and quite unusual hardware aid, macromodules. Of all the new areas emerging in Computer Science the teaching of computer structures, from an engineering viewpoint, has continually challenged the professional educator. This has in a sense presented a dilemma to him: for digital computer system design requires a broad look at a variety of configurations, but also seems to require a comprehensive examination of individual circuit details in order to remain in a practical atmosphere. As is well known, such detailed investigation of many systems is virtually impossible in the time allotted in most cirricula.

A modification of the conventional design method for pulse-type sequential logic is developed in which threshold gates are used in all of the combinational portions of the circuit. The canonical configuration, memory element employed, tabular design aids, etc., found in the conventional method were changed as necessary in order to use more effectively the unique properties possessed by threshold elements. A theorem providing insight for threshold gate realization is given and a classification of sequential functions is discussed in order to facilitate the understanding and use of the new process. Finally, examples are presented showing a significant advantage of the present method in both gate and transistor economy over conventional design.