Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Sumit Adhikari

dblp:91/9203 · DBLP profile ↗
← Back
6ranked-venue papers
4as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › system-level design
electronic system level design
0.312017
ESL Design in SystemC AMS: Introducing a top-down design methodology for mixed-signal systems: Invited · DAC 2017
Electronic design automation › hardware verification and test
hardware verification
0.312017
ESL Design in SystemC AMS: Introducing a top-down design methodology for mixed-signal systems: Invited · DAC 2017
Electronic design automation › system-level design
virtual prototyping
0.312017
ESL Design in SystemC AMS: Introducing a top-down design methodology for mixed-signal systems: Invited · DAC 2017

Methods — techniques the papers use, named apart from their topics

top-down design methodology · 0.3SystemC AMS · 0.3
YearPublicationVenuePosition
2017 ESL Design in SystemC AMS: Introducing a top-down design methodology for mixed-signal systems: Invited
abstract
For the design and verification of a heterogeneous system architecture containing analog, digital, and software functionality, the use of modern languages and advanced Electronic System-Level (ESL) top-down design methodologies becomes fundamental. This paper will present the industrial application of the SystemC analog/mixed-signal (AMS) extensions in combination with SystemC and other C++ libraries, to enable mixed-signal system-level design of a Magneto Resistive Sensor product. It will demonstrate an efficient top-down design and early verification approach by creating an accurate mixed-signal virtual prototype for concept development and architecture exploration, bringing high modelling fidelity and high simulation speed.
Martin Barnasconi, Sumit Adhikari
DAC2
2012 FAst optimization of analog amplifier architecture using simulated annealing
Sumit Adhikari, Florian Schupfer, Christoph Grimm 0001
FDL1
2011 High performance adaptive sensor interface design through model based estimation of analog non-idealities
abstract
Accurate and sufficient design of AMS signal paths is always being a challenge for system designers requiring high simulation performance of the analog model which also incorporates circuit level non-idealities. The new SystemC AMS extensions offer high simulation performance as well as capabilities of incorporating circuit level non-ideal effects. In this paper we modelled a low Over Sampling Ratio (OSR), second order Sigma Delta (ΣΔ) Analog to Digital Converter (ADC) which incorporates non-ideal effects like sampling jitter, kBT/CSnoise, switch non-linearities, band-gap noise and operational amplifier non-idealities (such as finite gain, finite bandwidth, gain nonlinearity, slew rate, leakage and saturation effect). The ADC shows a performance bottle neck of 16 bits. State-of-Art signal conditioning techniques use adaptive correction methods inside the analog part or inside the DSP part of the ADC making it more complicated to realize. In our design we have implemented the adaptive filtration within the micro-controller to correct the noise ground as well as large signal non-linear effects to produce an output which is 20-bits clean, proving sufficiency of low order and low OSR of a ΣΔ ADC for 20 bit resolution as well as a simplified adaptive filtration scheme alleviating the need of adaptive blocks within the ADC.
Sumit Adhikari, Jan Haase 0001, Christoph Grimm 0001
DDECS1
2011 Abstract modeling and simulation based selective estimation
abstract
SystemC AMS offers high abstraction and simulation speed through models of computation and language features such as static scheduling, constant time stepping, linear solver and dataflow paradigm. We demonstrate that such rich expressiveness can render non-ideal behavior in system level description. Design exploration and refinement from system level down to cycle accurate or circuit level is also demonstrated. The main contribution is that the fine grain characterization can start at system level design.
Yaseen Zaidi, Sumit Adhikari, Christoph Grimm 0001
DDECS2
2011 Abstract modelling and estimation of a high performance Tobey's PGA
Sumit Adhikari, Christoph Grimm 0001, Jan Haase 0001
FDL1
2010 Modeling Switched Capacitor Sigma Delta Modulator Nonidealities in SystemC-AMS
Sumit Adhikari, Christoph Grimm 0001
FDL1