In this paper, we present a dense hybrid proposal modulation (DHPM) method for lane detection. Most existing methods perform sparse supervision on a subset of high-scoring proposals, while other proposals fail to obtain effective shape and location guidance, resulting in poor overall quality. To address this, we densely modulate all proposals to generate topologically and spatially high-quality lane predictions with discriminative representations. Specifically, we first ensure that lane proposals are physically meaningful by applying single-lane shape and location constraints. Benefitting from the proposed proposal-to-label matching algorithm, we assign each proposal a target ground truth lane to efficiently learn from spatial layout priors. To enhance the generalization and model the inter-proposal relations, we diversify the shape difference of proposals matching the same ground-truth lane. In addition to the shape and location constraints, we design a quality-aware classification loss to adaptively supervise each positive proposal so that the discriminative power can be further boosted. Our DHPM achieves very competitive performances on four popular benchmark datasets. Moreover, we consistently outperform the baseline model on most metrics without introducing new parameters and reducing inference speed. The codes of our method are available athttps://github.com/wuyuej/DHPM.

This paper proposes a novel voltage scaling low-power design methodology for large system-on-chip (SoC) designs. It scales the supply voltage to a SoC based on operating conditions and bit error rate in a system. It allows occasional timing errors in the circuit and relies on a forward error correction that already exists in the system to correct the errors. As a result, the proposed technique imposes no hardware overhead yet yields significant power savings. More importantly, it does not require any circuit modification based on place and route, thus it is easy to implement and has no impact for time to market. The new technique was implemented in a complex telecom SoC design, and silicon measurements show power savings up to 50% for free.

Existing silicon validation techniques only address test data capture issues. They all assume the existence of live traffic in the system. Unfortunately, this is not always the case in real life. This paper proposes a novel design methodology for silicon validation and system integration. It uses built-in functional tests to simulate live traffic at full speed when a real one is not available at the arrival of the first silicon. The proposed methodology provides a platform upon which many silicon validation and system integration tasks can be performed before a real traffic is ready. It can also be used to cover logic corner cases that may not be easily achievable in real life. The proposed methodology has been proven effective on time-to-market and quality of verification with multiple complex system-on-chip designs.

Detection of open defects in static random access memory (SRAM) cells, including those causing data retention faults (DRFs), is known to be difficult and time consuming. This paper proposes a novel design-for-test (DFT) technique that allows SRAMs to be tested at full speed for these defects. As a result, it achieves not only significant test time reduction but also full coverage of open defects, including those undetectable to previous solutions. The proposed technique is referred to as predischarge write test mode (PDWTM). Implementation of the proposed technique requires little design effort and imposes negligible hardware and performance penalties. Furthermore, the proposed technique can be easily merged with any March algorithm, thus resulting in full DRF and other SRAM cell open defect coverage. The proposed technique has been validated by SPICE simulation using both low-power and high-speed SRAM cells.

This paper addresses the test power model problem for embedded SRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a single-rectangle power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of zero power consumption for the detection of Data Retention Faults. This paper takes advantage of this zero power period and proposes a retention-aware test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarious in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the zero power period is fully utilized in a SoC environment.

The paper proposes a diagnosis scheme aimed at reducing the diagnosis time of distributed small embedded SRAMs (e-SRAMs). This scheme improves on one proposed previously (Huang, D.C. et al., Proc. Int. Conf. VLSI Design, p.397-402, 2001; Huang and Jone, W.B., IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.21, no.4, p.449-65, 2002). The improvements are mainly twofold. On one hand, the diagnosis of time-consuming data retention faults (DRFs), which is neglected by the diagnosis architecture of Huang et al., is now considered and performed via a DFT technique referred to as the "no write recovery test mode" (NWRTM). On the other hand, a pair comprising a serial-to-parallel converter (SPC) and a parallel-to-serial converter (PSC) is utilized to replace the bidirectional serial interface, to avoid the problems of serial fault masking and defect rate dependent diagnosis. Results from our evaluations show that the proposed diagnosis scheme achieves an increased diagnosis coverage and reduces diagnosis time compared to those obtained by Huang et al., with negligible extra area cost.

Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typically time-consuming due to the required pause time that needs to be introduced in the test session. This paper proposes a novel technique, referred to as pre-discharge write test mode (PDWTM), that effectively integrates the testing of DRF within "regular" March algorithms such that the rate (speed) of the latter remains unaltered. That is, the PDWTM enables DRF testing without incurring the additional cycles or pauses in the March test execution thereby enabling additional coverage at no expense in terms of overall test time. We show that DRFs can be easily detected by pre-discharging bit lines before a write operation. Here, the PDWTM is evaluated using both high-speed and low power memory cells, representing two extreme cases based on the typical memory design methodologies.

Predesigned cores and reusable modules are popularly used in the design of large and complex application specific integrated circuits (ASICs). As the size and complexity of ASICs increase, the test effort, including test development effort, test data volume, and test application time, has also significantly increased. This paper shows that this test effort increase can be minimized for ASICs that consist of multiple identical cores. A novel design for testability (DFT) technique is proposed to test ASICs with identical embedded cores. The proposed technique significantly reduces test application time, test data volume, and test generation effort.

Time Domain Multiplex (TDM) SRAMs are a new type of multi-port SRAMs. Due to their small area and flexibility, they have found a wide range of applications in telecommunication ASICs. For a TDM SRAM, the memory core runs many times faster than the circuits that access it. In other words, the memory runs at an internal clock that is much faster than the system clock. This slow system clock coupled with the fast internal clock creates new challenges for at-speed testing of TDM SRAMs. This paper proposes a novel BIST solution for at-speed testing of TDM SRAMs with a slow system clock. The solution can be implemented with most commercial BIST controllers for conventional SRAMs. All the required modifications can be included in a modified memory collar The hardware addition is small. The test time is the same as that for a conventional multi-port SRAM of the same size.

In high speed systems, the AC performance of interconnects on boards and backplanes are critical. Today, most companies rely on functional test vectors to conduct interconnect delay fault tests. Besides poor fault coverage, this approach does not provide much diagnostic information when faults are detected. Based on the concept of early capture and late update, this paper proposes a novel technique to conduct board interconnect delay fault test using a IEEE 1149.1 standard TAP controller. The proposed technique does not require any extra pin to ASICs, does not require any modification of standard boundary scan cells and uses a standard TAP controller. The costs of the proposed technique include only a few flip-flops plus some gates in a TAP controller wrapper without modification of the standard TAP controller itself.

Existing built-in self-test (BIST) diagnostic techniques assume the existence of a few bit errors in a test response sequence. This assumption is unrealistic since in a BIST environment a single defect can usually cause hundreds or thousands of errors in a test response sequence. Without making the above assumption, this paper presents a novel BIST fault diagnostic technique for scan-based VLSI devices. Based on faulty signature information, our scheme guarantees correct identification of the scan flip-flops that capture errors during test, regardless of the number of errors the circuit may produce. In addition, it is able to identify failing test vectors with a better diagnostic capacity than existing techniques. The proposed scheme does not assume any specific fault model. Thus, it is applicable to all voltage-detectable faults. It also applies naturally to multifrequency BIST. This paper analyzes the efficiency of the scheme in terms of diagnostic coverage. Experimental results on several large ISCAS89 benchmark circuits and industrial circuits are also reported.

Most multi-port memory BIST algorithms treat the memory as multiple individual single-port memories and test each independently using the algorithms developed for single-port RAMs. A major problem with this approach is the lack of coverage for multi-port specific defects, such as inter-port interferences due to shorts across ports. This paper proposes a novel BIST algorithm for multi-port RAMs that detects both The conventional single-port faults as well as inter-port shorts. The proposed algorithm performs a conventional single-port test such as MARCH (1991) or SMARCH (1990) on one port of the memory and simultaneously performs an inter-port test on all other ports. The algorithm does not impose any extra test time and requires the addition of only a few gates to a conventional single-port BIST controller, independently of the size of the memory.

Existing BIST diagnostic techniques assume the existence of a very few bit errors in a test response sequence. This assumption is unrealistic since in a practical BIST environment a single defect in a circuit can usually cause hundreds or thousands of errors in a test response sequence. This paper presents a novel BIST fault diagnostic technique for scan-based VLSI devices, without making the above assumption. Based on faulty signature information our scheme guarantees correct identification of the scan flops that capture errors during test, regardless of the number of errors the circuit may produce. In addition, it is also capable of identifying the failing test vectors with a better diagnostic capacity than existing techniques. The proposed scheme does not assume any specific fault model. Thus, it is able to diagnose all voltage-detectable faults. This paper analyzes the efficiency of the scheme in terms of diagnostic coverage. Experimental results on several large ISCAS89 benchmark circuits and industrial circuits are also included.

Compared to single signature analysis, checking multiple intermediate signatures has many advantages, e.g., smaller aliasing, easier computation of exact fault coverage, and shorter average test time. Conventionally, checking n signatures requires n references. Storing these references and comparing them with collected signatures imposes considerable hardware requirements. In this paper, we propose a novel multiple intermediate signature analysis scheme which checks n signatures against a single reference, thus making the circuitry for checking n signatures essentially the same as that for checking only one. The cost for implementing the proposed scheme is a very small nonrecurring CPU time expenditure in the design phase with no CUT modifications. In return, the proposed scheme yields significant recurring silicon area savings as well as reduced aliasing, and consequently higher test quality. This paper also defines a property for linear compactors that guarantees the existence of an initial state that necessarily yields two identical signatures at arbitrary check points for all circuits.>

Proposes a new BIST multiple intermediate signature analysis scheme which checks n signatures against a single reference. Therefore, the circuitry for checking n signatures is essentially the same as that for checking one signature. The scheme is based on a manipulation of the CUT's fault-free output sequence. No circuit modification is required. The cost for implementing the scheme is a small nonrecurring CPU time expenditure in the design phase. In return, the scheme yields significant recurring silicon area savings, and reduced aliasing.>

Due to fanout in a circuit, the speed efficiency of existing path delay fault simulation algorithms suffers from redundant evaluations of many circuit nodes in the backtrace process of every simulation pass. This paper introduces two new concepts-subpath event sensitizability (SES) and subpath event sensitizability robustness (SESR). Based on these new concepts, the authors propose a new procedure for path delay fault simulation whereby each node of the simulated circuit is evaluated only once per simulation pass in the backtrace process. Experiments with the ISCAS'85 benchmark circuits show that the procedure accelerates path delay fault simulation significantly. The proposed procedure can be implemented for parallel pattern path delay fault simulation. The concepts of SES and SESR can also improve both CPU time and memory efficiency of path delay fault simulation if only a subset of all the paths is considered.>