The focus of this paper is to measure and qualify high-level process variation models by measuring variability on FPGAs. Measurements are done with high spatial resolution and demonstrate how the high-resolution data matches two industry test cases. The benefit of such an approach is that several inexpensive FPGAs, which are normally on the leading edge of technologies compared to ASICs, obviate the need of fabricating many custom test chips. Specifically, our evaluation shows how measurements of an Altera Cyclone II FPGA can be used to derive variability models for several 90nm commercial designs such as the Sun Niagara and Intel Pentium D. Even though the FPGAs and commercial processors are produced by different fabs (TSMC, TI, and Intel, respectively), we find the FPGAs to be very useful for predicting variation in the commercial processors.

Development of an autonomous surface vessel platform for marine sensing is presented. Much of the design characteristics are general, but a specific application related to monitoring of designated coastal marine protected areas is discussed. The sensor platform vessel described is small, approximately 35 lbs in air, and designed for low power requirements. The power requirements for propulsion are examined and show that an estimated 5 W average power is expected to be sufficient to operate the vessel at its maximum speed. Initial tests verify operation of the vessel's navigation algorithm to control heading in a sheltered harbor.

We report the design, prototype construction and initial testing of a small minibuoy that is aimed at use in a coordinated, wireless networked array of buoys for near-surface ocean sensing. This vehicle is designed to fill the gap between larger ocean surface vessels and/or moored buoys and subsurface gliders. The size and cost is low enough that these versatile sensor platforms can be deployed easily and in quantity. Since these minibuoys are mobile, they can keep station in currents as large as 25 cm/s or move as an adaptive, coordinated sensor array for high resolution in both time and space. The buoy is about 74 cm (29 in) long, 41 cm (16 in) wide (max) and weighs about 14.5 kg (32 lbs); hence, it can be deployed easily from small craft. Deployment times are about 1 to 2 days or more - longer with solar power. The buoy structure is fiberglass and PVC with two 2 W DC motors. Control is done with GPS and magnetic heading sensors and a PID scheme to maintain course. Communication is via a 900 MHz system with a range of 1 to 2 km and plans for a longer range HF/VHF or satellite system. The initial sensor system is designed for ocean hyperspectral observations as surface truth for airborne system calibration and validation and other ocean color applications. Acoustic, wave, air & water temperature sensors as well as GPS are included. The Mark I prototype has been successfully tested in a pool with manual control.

System design complexity is growing rapidly. As a result, current development costs are constantly increasing. It is becoming increasingly difficult to estimate how much time it will take to design and verify these designs, which are getting denser and increasingly more complex. To compound this problem, circuit design cost estimation still does not have a quantitative approach. Although designing a system is very resource consuming, there is little work invested in measuring, understanding, and estimating the effort required. To address part of the current shortcomings, this paper introduces μPCBComplexity, a methodology to measure and estimate PCB (printed circuit board) design effort. PCBs are the central component of many systems and require large amounts of resources to properly design and verify. μPCBComplexity consists of two main parts; a procedure to account for the contributions of the different elements in the design, and a non-linear statistical regression of experimental measures in order to determine a good design effort metric. We use μPCBComplexity to evaluate a series of design effort estimators for twelve PCB designs. By using the proposed μPCBComplexity metric, designers can estimate PCB design effort.

Microprocessor design complexity is growing rapidly. As a result, current development costs for top of the line processors are staggering, and are doubling every 4 years. As we design ever larger and more complex processors, it is becoming increasingly difficult to estimate how much time it will take to design and verify them. To compound this problem, processor design cost estimation still does not have a quantitative approach. Although designing a processor is very resource consuming, there is little work measuring, understanding, and estimating the effort required. To address this problem, this paper introduces /spl mu/Complexity, a methodology to measure and estimate processor design effort. /spl mu/Complexity consists of three main parts, namely a procedure to account for the contributions of the different components in the design, accurate statistical regression of experimental measures using a nonlinear mixed-effects model, and a productivity adjustment to account for the productivities of different teams. We use /spl mu/Complexity to evaluate a series of design effort estimators on several processor designs. Our analysis shows that the number of lines of HDL code, the sum of the fan-ins of the logic cones in the design, and a linear combination of the two metrics are good design effort estimators. On the other hand, power, area, frequency, number of flip-flops, and number of standard cells are poor estimators of design effort. We also show that productivity adjustments are necessary to produce accurate estimations.