Marcel D. van de Burgwal

dblp:92/1481 · DBLP profile ↗
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5ranked-venue papers
1as first author
2since 2021 · last 2024
0000-0003-0912-7131ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 61% Hardware accelerators and domain-specific architectures · 30% Integrated circuit design · 9%

Topics — the 2 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms › neuromorphic computing › neuromorphic vision
event-based vision
0.812024
Invited: Neuromorphic Vision Modalities in the NimbleAI 3D Chip · DAC 2024
Emerging computing paradigms
neuromorphic computing
0.812024
Invited: Neuromorphic Vision Modalities in the NimbleAI 3D Chip · DAC 2024

Methods — techniques the papers use, named apart from their topics

spiking neural network · 0.8selective visual attention · 0.8
YearPublicationVenuePosition
2024 Invited: Neuromorphic Vision Modalities in the NimbleAI 3D Chip
abstract
This paper provides an overview of the ongoing work to enable novel modalities of passive monocular neuromorphic vision in the NimbleAI sensing-processing architecture; namely, foveated and light-field event-driven vision with selective visual attention. The latter vision modality encodes 3D visual surroundings as sparse visual events in a 4D spatiotemporal domain, adding depth to current representation of visual information delivered by Dynamic Vision Sensors (DVS). The NimbleAI architecture implements hardware support for efficient execution of mainstream computer vision algorithms and AI models using these visual inputs. The architecture is designed to harness the latest advancements in 3D silicon integration, making it possible to squeeze sensing and spiking circuitry, memory, and processing engines into a miniature silicon volume.
Xabier Iturbe, Bernabé Linares-Barranco, Sio-Hoi Ieng, Arne Erdmann, Luca Peres, Oliver Rhodes, Rafael Tornero, Manolis Sifalakis, Marcel D. van de Burgwal, Amirreza Yousefzadeh, Maha Kooli, Riccardo Alidori, Pavel Zaykov
DAC9
2023 NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips
abstract
The NimbleAI Horizon Europe project leverages key principles of energy-efficient visual sensing and processing in biological eyes and brains, and harnesses the latest advances in$\mathbf{33D}$stacked silicon integration, to create an integral sensing-processing neuromorphic architecture that efficiently and accurately runs computer vision algorithms in area-constrained endpoint chips. The rationale behind the NimbleAI architecture is: sense data only with high information value and discard data as soon as they are found not to be useful for the application (in a given context). The NimbleAI sensing-processing architecture is to be specialized after-deployment by tunning system-level trade-offs for each particular computer vision algorithm and deployment environment. The objectives of NimbleAI are: (1)$\mathbf{100x}$performance per mW gains compared to state-of-the-practice solutions (i.e., CPU/GPUs processing frame-based video); (2)$\mathbf{50x}$processing latency reduction compared to CPU/GPUs; (3) energy consumption in the order of tens of mWs; and (4) silicon area of approx. 50 mm2.
Xabier Iturbe, Nassim Abderrahmane, Jaume Abella 0001, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández 0001, Daniele Ielmini, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noël, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov
DATE46
2011 Mixed continuous/discrete time modelling with exact time adjustments
abstract
Many systems interact with their physical environment. Design of such systems need a modelling and simulation tool which can deal with both the continuous and discrete aspects. However, most current tools are not adequately able to do so, as they implement both continuous and discrete time signals as consisting of separate values at a single global simulation clock. The consequence is that simulation, of a time delay for example, either yields inaccurate results or becomes inefficient.
Kenneth C. Rovers, Jan Kuper, Marcel D. van de Burgwal, André B. J. Kokkeler, Gerard J. M. Smit
IWCMC3
2010 Adaptive Beamforming Using the Reconfigurable MONTIUM TP
abstract
Until a decade ago, the concept of phased array beam forming was mainly implemented with mechanical or analog solutions. Today, digital hardware has become powerful enough to perform the massive number of operations required for real-time digital beam forming. While more and more applications are using beam forming to improve the communication channel utilization both in space and frequency, many dedicated digital architectures are proposed for the processing. By using a reconfigurable architecture, the same hardware platform can be reused for different applications with different processing needs. In this paper, we present a reconfigurable Multi-processor System-on-Chip based solution for phased array processing that supports advanced tracking mechanisms to continuously receive signals with a mobile receiver. An adaptive beam former for DVB-S satellite reception is presented, that uses a Constant Modulus Algorithm to track satellites. The processing of a receiver with 64 antennas and 3 beams is mapped on a reconfigurable processor named Montium TP. The total implementation of such a receiver requires about 570 clock cycles on a single Montium TP, but can also be partitioned over multiple Montium TPs to support larger phased arrays.
Marcel D. van de Burgwal, Kenneth C. Rovers, Koen C. H. Blom, André B. J. Kokkeler, Gerard J. M. Smit
DSD1
2010 DVB-S Signal Tracking Techniques for Mobile Phased Arrays
abstract
A system that uses adaptive beamforming techniques for mobile DVB-S reception is proposed in this paper. The purpose is to enable DVB-S reception in moving vehicles. Phased arrays are able to electronically track the desired signal during dynamic behaviour of the vehicle the array is mounted on. The proposed system uses blind beamforming to adapt the array steering vector to changing signal (conditions and) directions. Movement of the vehicle, the phased array is mounted on, leads to modulus and phase deviations at the beamformer output. An extended version of the CMA algorithm is used to adapt the steering vector weights to compensate for those deviations. For simulation of the proposed system a model of vehicle dynamics is used to generate realistic antenna data. Simulation of the proposed system based on this antenna data shows appropriate corrections for modulus and phase deviations.
Koen C. H. Blom, Marcel D. van de Burgwal, Kenneth C. Rovers, André B. J. Kokkeler, Gerard J. M. Smit
VTC Fall2