Demo Data from VLDB 2026 / reviewers in the wild / expert
Stelios Neophytou
dblp:92/2052 · also Stelios N. Neophytou
· DBLP profile ↗
18ranked-venue papers
11as first author
1since 2021 · last 2025
0000-0001-5728-6845ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 17 · 11 first-author · 1 since 2021Security and privacy · 1Software engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 68% Parallel and multicore computing · 32% |
Topics — the 10 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.5 | 2 | 2019 | Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques · IEEE Trans. Computers 2010 |
Electronic design automation › hardware verification and test
fault simulation |
0.4 | 1 | 2019 | Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 |
Electronic design automation › hardware verification and test › fault simulation
parallel fault simulation |
0.4 | 1 | 2019 | Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 |
Parallel and multicore computing
parallel programming models and runtimes |
0.4 | 1 | 2019 | Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 |
Parallel and multicore computing › parallel programming models
shared-memory parallelization |
0.4 | 1 | 2019 | Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 |
Electronic design automation › hardware verification and test › design for testability
built-in self-test |
0.1 | 1 | 2010 | Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques · IEEE Trans. Computers 2010 |
Electronic design automation › hardware verification and test
test generation |
0.1 | 1 | 2010 | Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques · IEEE Trans. Computers 2010 |
Electronic design automation
hardware test |
0.1 | 1 | 2006 | Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Electronic design automation › hardware verification and test › delay fault testing
transition fault testing |
0.1 | 1 | 2006 | Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Electronic design automation › hardware verification and test › test data compression
test set embedding |
0.0 | 1 | 2010 | Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques · IEEE Trans. Computers 2010 |
Methods — techniques the papers use, named apart from their topics
multicore parallelization · 0.4fault dropping · 0.4hierarchical fault-compatibility algorithm · 0.1LFSR reseeding · 0.1quality test function derivation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | European Test Symposium Teams: an Anniversary SnapshotabstractThe IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing. Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi 0002, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. D. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard 0001, Marcello Traiola, Arnaud Virazel, Fernando Santos 0001, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Veiras Bolzani, Milos Krstic, Marko S. Andjelkovic, Fabian Vargas 0001, Grigor Tshagharyan, Gurgen Harutunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zainalabedin Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand |
ETS | 36 |
| 2020 | Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems
Stavros Hadjitheophanous, Stelios Neophytou, Maria K. Michael |
IEEE Trans. Very Large Scale Integr. Syst. | 2 |
| 2019 | Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore SystemsabstractCurrent and future multicore architectures can significantly accelerate the performance of test automation procedures depending on the underlying architecture and the scalability of their algorithms. This paper proposes a new parallel methodology targeting the fault simulation problem, for shared memory multicore systems, that maintains scalability with the increase of the number of cores. The method is based on a simple single thread process that allows focusing on the optimization of the parallelization process in different dimensions. Additionally, a number of optimizations are incorporated in the approach to control fault dropping and to avoid unnecessary work. The reported experimental results, for both random and deterministic test sets, demonstrate the scalability of the method. As the number of cores increases, the reported speed-up increases proportionally, where comparable recent methods report saturation or even reduction of the obtained speed-up. Stavros Hadjitheophanous, Stelios Neophytou, Maria K. Michael |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2018 | Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering
Stelios Neophytou, Maria K. Michael |
J. Electron. Test. | 1 |
| 2016 | Utilizing shared memory multi-cores to speed-up the ATPG processabstractA new test generation methodology is proposed that takes advantage of shared memory multi-core systems. Appropriate parallelization of the main steps of ATPG allocates resources in order to minimize workload duplication and multi-threading race contention, often encountered in parallel implementations. The proposed approach ensures that the obtained acceleration grows linearly with the number of processing cores and, at the same time, keeps the test set size close to that obtained by serial ATPG. The experimental results demonstrate that the proposed methodology achieves higher degree of speed-up than comparable state-of-the-art multi-core based tools, while maintains similar test set sizes. Stavros Hadjitheophanous, Stelios Neophytou, Maria K. Michael |
ETS | 2 |
| 2016 | Scalable parallel fault simulation for shared-memory multiprocessor systemsabstractMulticore architectures can significantly accelerate the performance of well-established design and test automation processes, provided that the underlying process is scalable with respect to the system on which it is executed. In this work we concentrate on fault simulation and propose a new parallel process for shared-memory multicore systems, capable of maintaining its scalability as the number of processing cores utilized increases. In order to maximize parallelization, the method utilizes a simple, non-optimized single thread simulation process, which allows for high degrees of freedom to be exploited by three different and combined dimensions of parallelism. Simulation data is distributed to the available cores in a balanced fashion in order to favor speed-up over single-core executions and, ultimately, scalability. The experimental results show that the proposed approach achieves high speed-up rates which, in contrast to comparable state-of the-art methods, increase monotonically with the number of cores demonstrating a highly scalable solution. Stavros Hadjitheophanous, Stelios Neophytou, Maria K. Michael |
VTS | 2 |
| 2015 | Tackling the complexity of exact path delay fault grading for path intensive circuitsabstractThe high accuracy of the Path Delay Fault model (PDF) is usually sidelined by its high complexity since the number of possible faults can become exponential to the circuit size (even when only critical faults are considered). Thus, fault simulation may require prohibitively large memory resources. In this work we propose a test reordering technique to control the complexity of exact PDF grading when Zero-suppressed Binary Decision Diagrams are used for fault representation. Experimentation on path dense benchmark circuits demonstrates considerable reduction in memory requirements for the PDF grading problem. Stelios Neophytou, Maria K. Michael |
ETS | 1 |
| 2014 | Processing and Communications Rate Requirements in Sensor Networks for Physical Thread Assessment
Ioannis Kyriakides, Stelios Neophytou, Anastasis Kounoudes, Konstantinos Michail, Yiannis Argyrou, Thomas Wieland |
CRITIS | 2 |
| 2014 | Optimal variable ordering in ZBDD-based path representations for directed acyclic graphsabstractThis work proposes a reverse topological ordering for the variables of Zero-suppressed Binary Decision Diagrams (ZBDD) which bounds their size when used to represent the paths of a Directed Acyclic Graph (DAG). Specifically, the size of a ZBDD representing all paths of a DAG is shown to be linear to the number of the edges in the DAG. Stelios Neophytou, Maria K. Michael |
ICCD | 1 |
| 2012 | A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits
Stelios Neophytou, Kyriakos Christou, Maria K. Michael |
J. Electron. Test. | 1 |
| 2012 | Test Pattern Generation of Relaxed n-Detect Test SetsabstractWhile defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as multiple detect orn-detect test sets, are of increased quality for a number of common defects in deep sub-micrometer technologies. Method for multiple detect test generation usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in a multiple detect (n-detect) test set, while preserving the original fault coverage. The experimental results demonstrate that the number of specified bits in, even compact,n-detect test sets can be significantly reduced without any impact on then-detect property. Additionally, in many cases, the size of the test set is reduced. Stelios Neophytou, Maria K. Michael |
IEEE Trans. Very Large Scale Integr. Syst. | 1 |
| 2011 | An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment EnumerationabstractThe correlation between the physical paths of a digital circuit has important implications in various design automation problems, such as timing analysis, test generation and diagnosis. When considering the complexity and tight timing constraints of modern circuits, this correlation affects both the design process and the testing approaches followed in manufacturing. In this work we quantify the diversity of a set of paths (or path segments), let these be critical I/O paths, error propagation paths for various fault models, or paths traced for diagnostic purposes. Circuit paths are encoded using Zero-Suppressed Binary Decision Diagrams (ZBDDs), the proposed method consists of a sequence of standard ZBDD operations to provide a measure of the overlap of the paths under consideration. The main contribution of the presented method is that, path or path segment enumeration is entirely avoided and, hence, a large number of paths can be considered in practical time. Experimentation using standard benchmark circuits demonstrates the effectiveness of the approach in showing the difference in path correlation between various critical I/O path sets. Stelios Neophytou, Kyriakos Christou, Maria K. Michael |
ETS | 1 |
| 2010 | Identification of critical primitive path delay faults without any path enumerationabstractIt has been previously shown that in order to guarantee the temporal correctness of a circuit, only the primitive path delay fault set needs to be tested. However, as in the case of the traditional and simpler path delay fault model, the number of possible faults can be exponential to the circuit size and, therefore, it is only practical to consider the set of critical faults. This work defines critical primitive path delay faults and presents an exact algorithm to identify them, using zero-suppressed binary decision diagrams and newly introduced operators necessary for handling multiple path delay faults. We report the number of critical primitive path delay faults for various criticality thresholds under the bounded delay model. The results indicate that only a small, but still necessary, number of multiple (primitive) faults, which escape testing under the singly testable fault criterion, must be considered in order to guarantee the timing correctness of the circuit. Kyriakos Christou, Maria K. Michael, Stelios Neophytou |
VTS | 3 |
| 2010 | Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic TechniquesabstractThis work presents two new methods for the generation of test sets with a small number of specified bits. Such type of test sets have been proven beneficial to a large number of test-related applications such as deterministic BIST, low power testing and test set enrichment. The first technique is static, since it considers an initial test set which attempts to relax via test replacement with tests of similar coverage but with fewer specified bits. The second technique is dynamic; it generates a test set from a zero base using a hierarchical fault-compatibility algorithm. Both methods are applicable to any enumerative fault method (linear to the circuit size). The experiments performed using the stuck-at fault model demonstrate the superiority of the proposed methods over comparable existing techniques, in reducing the total number of specified bits per generated test set. The applicability of the generated relaxed test sets is demonstrated for one, out of the many, possible applications, that of deterministic test set embedding. A general framework that integrates the proposed relaxation methods in two popular LFSR-based test set embedding schemes (full and partial reseeding), along with a systematic exploration of related parameters, is proposed. The obtained results show significant reductions in seed storage requirements. Stelios Neophytou, Maria K. Michael |
IEEE Trans. Computers | 1 |
| 2008 | On the Relaxation of n-detect Test SetsabstractWhile defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as n-detect test sets, are of increased quality for a number of common defects in deep sub-micron technologies, n-detect test generation methods usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in an n-detect test set, while preserving the n-detection property, in contrast to any other existing test set relaxation method. The experimental results demonstrate that the number of specified bits in, even compact, n- detect test sets can be significantly reduced without any impact on the n-detect property. Stelios Neophytou, Maria K. Michael |
VTS | 1 |
| 2006 | Efficient Deterministic Test Generation for BIST Schemes with LFSR ReseedingabstractWe propose a novel method for generating test patterns that can be encoded efficiently using reseeding of LFSR-based schemes for hybrid BIST. Our focus is to reduce the number of deterministic tests while keeping their overall number of specified bits small and, thus, reduce the storage requirements for the LFSR seeds. The proposed solution is based on test function manipulation and generates a compact test set in which individual tests have a high number of unspecified bits. The method uses binary decision diagrams (BDDs) and a modified version of the min-cost max-matching problem on graphs. The obtained experimental results clearly demonstrate the impact of the proposed ATPG algorithm in reducing the on-chip seed storage, when combined with the considered BIST schemes Stelios Neophytou, Maria K. Michael, Spyros Tragoudas |
IOLTS | 1 |
| 2006 | Functions for Quality Transition-Fault Tests and Their Applications in Test-Set EnhancementabstractA method to implicitly derive all tests for each transition fault under established fault-sensitization criteria is presented. The derived quality test functions are enhanced in three different ways to derive better quality test sets. One enhancement restricts fault sensitization along critical subcircuits whose paths have long delays under a fixed-delay model. Another manipulates the functions to generate compact test sets. The last one enriches the test set with additional test vectors so that transition faults are tested through several activation and propagation paths without path enumeration. Experimental results demonstrate the effectiveness of deriving such enhanced test functions Stelios Neophytou, Maria K. Michael, Spyros Tragoudas |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2005 | Test set enhancement for quality transition faults using function-based methodsabstractA recent method generates high quality tests for transition faults using functions. Event sensitization criteria as well as path lengths can be taken into consideration during the generation of such test functions. It is shown how to manipulate the test functions to generate compact test sets. Experimental results on ISCAS'85 and ISCAS'89 circuits show that a compaction rate of the order of 70% to 84% is achieved without compromising fault coverage. Moreover, a novel method to enrich the compacted test set with additional vectors is presented so that transition faults are tested through different activation and propagation paths. Such test sets havehigher quality, compared to traditional transition fault test sets, since events propagate through many critical paths. Stelios Neophytou, Maria K. Michael, Spyros Tragoudas |
ACM Great Lakes Symposium on VLSI | 1 |