VLDB 2026 Research / reviewers in the wild / expert
C. L. Chen
dblp:92/2126
· DBLP profile ↗
14ranked-venue papers
11as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 9 · 7 first-authorTheory of computation · 4 · 4 first-authorArtificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
10 papers |
Coding theory · 100% Algorithms and data structures · 0% | |
| Computer architecture, parallel and distributed computing, and storage systems
7 papers |
Electronic design automation · 63% Memory systems · 18% Energy-efficient computing · 10% |
Topics — the 18 heaviest of 19, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Coding theory › error-correcting codes
cyclic codes |
0.0 | 2 | 1999 | On a (145, 32) binary cyclic code · IEEE Trans. Inf. Theory 1999 Exhaustive Test Pattern Generation Using Cyclic Codes · IEEE Trans. Computers 1988 |
Coding theory › error-correcting codes › cyclic codes
binary cyclic code |
0.0 | 1 | 1999 | On a (145, 32) binary cyclic code · IEEE Trans. Inf. Theory 1999 |
Electronic design automation › power integrity
switching noise |
0.0 | 1 | 1996 | Switching Codes for Delta-I Noise Reduction · IEEE Trans. Computers 1996 |
Coding theory › error-correcting codes
error detection and correction |
0.0 | 1 | 1996 | Switching Codes for Delta-I Noise Reduction · IEEE Trans. Computers 1996 |
Electronic design automation
hardware test |
0.0 | 2 | 1988 | Exhaustive Test Pattern Generation Using Cyclic Codes · IEEE Trans. Computers 1988 Linear Dependencies in Linear Feedback Shift Registers · IEEE Trans. Computers 1986 |
Coding theory › error-correcting codes › error detection and correction
symbol error-correcting codes |
0.0 | 1 | 1992 | Symbol Error-Correcting Codes for Computer Memory Systems · IEEE Trans. Computers 1992 |
Energy-efficient computing › dynamic power reduction
switching activity reduction |
0.0 | 1 | 1996 | Switching Codes for Delta-I Noise Reduction · IEEE Trans. Computers 1996 |
Memory systems
semiconductor memory |
0.0 | 2 | 1986 | Error-Correcting Codes for Semiconductor Memories · ISCA 1984 Byte-Oriented Error-Correcting Codes for Semiconductor Memory Systems · IEEE Trans. Computers 1986 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1986 | Linear Dependencies in Linear Feedback Shift Registers · IEEE Trans. Computers 1986 |
Coding theory › error-correcting codes › burst error correction
byte error-correcting codes |
0.0 | 1 | 1986 | Byte-Oriented Error-Correcting Codes for Semiconductor Memory Systems · IEEE Trans. Computers 1986 |
Hardware reliability and fault tolerance › error correction
error-correcting codes |
0.0 | 1 | 1984 | Error-Correcting Codes for Semiconductor Memories · ISCA 1984 |
Memory systems › magnetic memory
magnetic bubble memory |
0.0 | 1 | 1978 | On the Generation of Permutations in Magnetic Bubble Memories · IEEE Trans. Computers 1978 |
Coding theory
linear feedback shift register |
0.0 | 1 | 1986 | Linear Dependencies in Linear Feedback Shift Registers · IEEE Trans. Computers 1986 |
Hardware reliability and fault tolerance
soft errors |
0.0 | 1 | 1984 | Error-Correcting Codes for Semiconductor Memories · ISCA 1984 |
Coding theory › error-correcting codes › combinatorial coding theory
finite geometry codes |
0.0 | 1 | 1972 | On Shortened Finite Geometry Codes · Inf. Control. 1972 |
Algorithms and data structures › combinatorial algorithms › enumeration algorithms
permutation generation |
0.0 | 1 | 1978 | On the Generation of Permutations in Magnetic Bubble Memories · IEEE Trans. Computers 1978 |
Coding theory › error-correcting codes › block codes › linear code
polynomial codes |
0.0 | 1 | 1969 | Further Results on Polynomial Codes · Inf. Control. 1969 |
Coding theory › error-correcting codes › block codes › linear code
quasi-cyclic codes |
0.0 | 1 | 1969 | Some Results on Quasi-Cyclic Codes · Inf. Control. 1969 |
Methods — techniques the papers use, named apart from their topics
coding theory · 0.0code construction · 0.0punctured cyclic codes · 0.0linear feedback shift register · 0.0probability analysis of linear dependence · 0.0permutation generation algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | A Scalable Multi-tier Architecture for the National Taiwan University Hospital Information System based on HL7 StandardabstractThis article describes the successful experiences of National Taiwan University Hospital (NTUH) in moving from IBM Mainframe to connected networking computer systems. We use multi-tier architecture and HL7 standard to implement our new outpatient hospital information system (HIS). The NTUH HIS is a complex environment with several operating systems, databases, and information systems. We adopt service-oriented architecture (SOA) to reduce the complex relations between systems and solve data consistency problems among databases. We also show that the distributed architecture can provide us stable and reasonable system performances. Our main contribution is proving that the distributed environment with HL7 standard and SOA can sustain in a highly demanding environment Tzu-Hsiang Yang, Po-Hsun Cheng, C. H. Yang, Feipei Lai, C. L. Chen, Hsiu-Hui Lee, Kai-Ping Hsu, Chi-Huang Chen, Ching-Ting Tan, Yeali S. Sun |
CBMS | 5 |
| 1999 | On a (145, 32) binary cyclic codeabstractWe discovered that a (145, 32) binary cyclic code generated by the product of an irreducible polynomial of degree 28 with exponent 145 and the polynomial x/sup 4/+x/sup 3/+x/sup 2/+x+1 has a minimum distance of 44. C. L. Chen |
IEEE Trans. Inf. Theory | 1 |
| 1996 | Switching Codes for Delta-I Noise ReductionabstractIn this paper, we address the off-chip driver delta-I or switching noise problem. We propose a novel approach based on switching codes to reduce this noise. These codes are designed to lower the number of drivers which switch in any given system cycle. A formal theoretic framework for switching codes is developed which provides an upper bound on the number of switching drivers as a function of bit width of the data bus and number of redundant switch bits. Switching codes with error detecting and error correcting capabilities are also presented. Switching codes also reduce the average switching activity and power consumed by the off-chip drivers. C. L. Chen, Brian W. Curran |
IEEE Trans. Computers | 1 |
| 1992 | Symbol Error-Correcting Codes for Computer Memory SystemsabstractA method is presented of constructing symbol error correcting codes that have a minimum symbol distance of 4. The method yields some codes that are more efficient than previously known codes. The application is to designing fault-tolerant semiconductor memories.> C. L. Chen |
IEEE Trans. Computers | 1 |
| 1990 | An Optimal Parallel Algorithm for Minimum Coloring of Intervals
Ming-Shing Yu, C. L. Chen, Richard C. T. Lee |
ICPP (3) | 2 |
| 1989 | Optimal Parallel Circle-Cover and Independent Set Algorithms for Circular-Arc Graphs
Ming-Shing Yu, C. L. Chen, Richard C. T. Lee |
ICPP (3) | 2 |
| 1988 | Exhaustive Test Pattern Generation Using Cyclic CodesabstractThe generation of exhaustive test patterns for VLSI circuits using linear feedback shift registers is described in terms of cyclic codes. Punctured cyclic codes are used to generate exhaustive test patterns of any length. A techniques for the generation of punctured cyclic codes is presented. A technique is also presented to reduce the size of test sets obtained from punctured cyclic codes.> C. L. Chen |
IEEE Trans. Computers | 1 |
| 1986 | Byte-Oriented Error-Correcting Codes for Semiconductor Memory SystemsabstractByte-oriented error-correcting codes are useful in correcting and detecting errors in a memory system organized in multiple-bit-perchip fashion. This paper presents the construction of new single-byte error-correcting and double-byte error-detecting codes. C. L. Chen |
IEEE Trans. Computers | 1 |
| 1986 | Linear Dependencies in Linear Feedback Shift RegistersabstractLinear feedback shift registers have been proposed to generate test patterns for the self-test of logic networks. The probability of linear dependence among k bit positions of a subset of k bits in a maximum length shift register sequence is an outstanding problem. In this correspondence, we derive a formula for the calculation of the probability. C. L. Chen |
IEEE Trans. Computers | 1 |
| 1984 | Error-Correcting Codes for Semiconductor Memories
C. L. Chen |
ISCA | 1 |
| 1978 | On the Generation of Permutations in Magnetic Bubble MemoriesabstractA better algorithm is presented for the generation of an arbitrary permutation in a model of magnetic bubble memories that have been investigated previously. C. L. Chen |
IEEE Trans. Computers | 1 |
| 1972 | On Shortened Finite Geometry Codes
C. L. Chen |
Inf. Control. | 1 |
| 1969 | Further Results on Polynomial Codes
C. L. Chen, Shu Lin 0001 |
Inf. Control. | 1 |
| 1969 | Some Results on Quasi-Cyclic Codes
C. L. Chen, W. Wesley Peterson, E. J. Weldon Jr. |
Inf. Control. | 1 |