An on-board UAV high-performance collision avoidance system sets up drastic constraints, which can be fulfilled by using carefully optimized many-core computational architectures. We report here a case study, where we implemented a many-core processor system, which can process a 100 megapixels/sec video flow, identifying remote airplanes, tracking flying objects by implementing computationally intensive Kalman filters. The introduced processor system is implemented in Spartan 6 FPGA, and consumes less than 1W.

In this paper, we propose a memristor bridge circuit consisting of four identical memristors that is able to perform zero, negative, and positive synaptic weightings. Together with three additional transistors, the memristor bridge weighting circuit is able to perform synaptic operation for neural cells. It is compact as both weighting and weight programming are performed in a memristor bridge synapse. It is power efficient, since the operation is based on pulsed input signals. Its input terminals are utilized commonly for applying both weight programming and weight processing signals via time sharing. In this paper, features of the memristor bridge synapses are investigated using the TiO memristor model via simulations.

There is a large variety of multi- and many-core platforms but established design methodologies for such processor arrays are still missing. We propose the concept of virtual cellular machine as an architecture, which does not correspond necessarily to a physical device, built according to the specific requirements needed by the programmer. The features of a virtual cellular machine (processors, memories etc.) can then be mapped onto existing physical many-core processors.

Unmanned Arial Vehicles (UAVs) require the development of some on-board safety equipments before inheriting the sky. An on-board collision avoidance system is being built by our team. Due to the strict size, weight, power, and costs constraints, visual intruder airplane detection is the only option. This paper introduces our visual airplane detector algorithm, which is designed to be operational in clear and in cloudy situations under regular daylight visual conditions. To be able to implement the algorithm on-board, we have carefully selected topographic operators, which can be efficiently solved on cellular processor arrays.

Oscillatory networks, their archetype being the Turing morphogenesis model, are mathematically represented by large systems of ordinary differential equations and provide an appropriate paradigm for describing many spatial-temporal periodic patterns. The aim of this manuscript is to show that locally connected oscillatory networks (oscillatory CNNs) with linear memoryless and space-invariant interactions may behave as globally connected networks with linear dynamical interactions, if some suitable components of the oscillator state vector are coupled. Space-invariant local connectivity allows to build simple prototype hardware platforms for processing spatial-temporal patterns.

The analysis and the detection of spatial-temporal patterns are extremely important to unfold the main features of numerous biological phenomena. It is also essential to conceive hardware oriented architectures in order to realize VLSI platforms that are able to process and recognize spatial-temporal patterns without breaking them into frames. Oscillatory networks, whose dynamical behavior is described by large system of ordinary differential equation, represent a suitable paradigm to describe many spatial-temporal time-periodic patterns. The aim of the manuscript is to show that locally connected oscillatory networks (oscillatory CNNs) with linear memoryless and space-invariant interactions act as globally connected oscillatory networks with linear dynamical interactions under the constraint that the couplings involve at least two components of the oscillator state vector. The space-invariant local connectivity permits to realize simple prototype hardware platforms for processing spatial-temporal patterns.

The ASIC implementation of a digital cellular visual microprocessor architecture is introduced. The processor array is constructed of simple, locally interconnected 8 bit microprocessors, operating in an extended SIMD mode. The processor array can be equipped with on-chip photo diode array, using 3D integration technology

In spite of the impressive advances related to retinal prostheses, there is no imminent promise to make them soon available with a realistic performance to help navigating blind persons. In our new project, we are designing a Bionic Eyeglass that is providing a wearable TeraOps visual computing power to advice visually impaired people in their daily life. In this paper the system aspects are explained. There are three different types of situations (home, office, street) and a few standard image flows (with some auditory information). The basic tasks are indoor and outdoor events, defined by blind people. Two types of cellular wave computing algorithms are used: general purpose spatial-temporal event detection by analogic subroutines developed so far, and recently developed multi-channel mammalian retinal model followed by a classifier. Typical indoor and outdoor event detection processes are being considered

Cellular wave computers and cellular nonlinear network (CNN) technology are discussed in this paper. It is a system-on-chip (SoC) architecture with xK processors and sensor arrays. The architectural lessons from the trends in manufacturing billion component devices when crossing the threshold of 100 nm feature size will determine the architecture, the elementary instructions, and the type of algorithms needed, hence also the complexity of the solution.

We introduce some CNN and analogic feature extraction algorithms for artificial immune systems, which are able to convert grayscale or color to binary images storing as much information as possible for further processing. We define a statistical property called immune histogram based on sub-patterns of these images. Our results and measurements show that these algorithms can be implemented in real-time applications. A sample application, which detects new textures in a familiar environment, is also presented.

Presents the welcome message from the conference proceedings.

In this paper we propose some biologically motivated local image sensor adaptation methods. The special feature of these methods is that they change the integration time of the imager on the pixel level. Using these methods, low dynamic range integration type CMOS sensors will be able to perceive high dynamic range scenes, and at the same time, compress their dynamic range by keeping high contrast and without introducing non-existing edges.

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 /spl mu/m CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.

This paper outlines motivations and models underlying the design of visual microprocessors based on the cellular neural network universal machine. We also overview the state of the art regarding the realization of these microprocessors in the form of very large-scale integration chips. Examples corresponding to measurements realized on these chips are enclosed for illustration purposes.

While in most application areas digital processors can solve problems initially, in some fields their capabilities are very limited. A typical example is vision. Simple animals outperform super-computers in the realization of basic vision tasks. In order to overcome the limitations of these conventional systems, a fundamentally different array architecture is needed. This architecture is based on the new paradigm of analogic cellular (CNN) computing whose most advanced implementation is the so-called CNN universal machine (CNN-UM). Its main components are: a) parallel architecture consisting of an array of locally-connected analog processors; b) a means of storing, locally, pixel-by-pixel, the intermediate computation results, and c) stored on-chip programmability. When implemented as a mixed-signal VLSI chip, the CNN-UM is capable of image processing at rates of trillions of operations per second with very small size and low power consumption. On the other hand, when integrating the adaptive multi-sensor array in the CNN-UM, the resulting sensor+computer array offers unprecedented capabilities. This paper reviews the latest results on CMN-UM chips and systems, and outlines the envisaged roadmap for these computers.

The objective of this paper is to provide a framework for the implementation of programmable Opto-Electronic Analogic CNN (POAC) Computers embedding CNN Universal Chips. Specifically, a new method for optical CNN implementation is provided and some details are experimentally studied. The POAC architecture includes the integration of an optical processing system, such as a joint transform correlator, with the fast spatio-temporal processing capabilities of a CNN-UM chip. We have built and tested an optical sub-unit of this experimental optoelectronic architecture to examine their processing capabilities for complex target recognition tasks. Preliminary result of these measurements will also be presented. The main idea is to introduce stored programmability into optical computing.

In this study, we present the initial results of cellular neural network (CNN)-based autowave metric to high-speed pattern recognition of gray-scale images. the application is to a problem involving separation of metallic wear debris particles from air bubbles. This problem arises in an optical-based system for determination of mechanical wear. This paper focuses on distinguishing debris particles suspended in the oil flow from air bubbles and aims to employ CNN technology to create an online fault monitoring system. For the class of engines of interest bubbles occur much more often than debris particles and the goal is to develop a classification system with an extremely low false alarm rate for misclassified bubbles. The designed analogic CNN algorithm detects and classifies single bubbles es and bubble groups using binary morphology and autowave metric. The debris particles are separated based on autowave distances computed between bubble models and the unknown objects. Initial experiments indicate that the proposed algorithm is robust and noise tolerant and when implemented on a CNN universal chip it provides a solution in real time.

Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided medical diagnosis, or telesurgery require an enormous computing power-in the order of trillions of operations per second (TeraOPS). Compared with conventional digital technology, cellular neural/nonlinear network (CNN)-based computing is capable of realizing these TeraOPS-range image processing tasks in a cost-effective implementation. To exploit the computing power of the CNN Universal Machine (CNN-UM), the CNN chipset architecture has been developed-a mixed-signal hardware platform for CNN-based image processing. One of the nonstandard components of the chipset is the cache memory of the analog array processor, the analog random access memory (ARAM). This paper reports on an ARAM chip that has been designed and fabricated in a 0.5-/spl mu/m CMOS technology. This chip consists of a fully addressable array of 32/spl times/256 analog memory registers and has a packing density of 637 analog-memory-cells/mm/sup 2/. Random and nondestructive access of the memory contents is available. Bottom-plate sampling techniques have been employed to eliminate harmonic distortion introduced by signal-dependent feedthrough. Signal coupling and interaction have been minimized by proper layout measures, including the use of protection rings and separate power supplies for the analog and the digital circuitry. This prototype features an equivalent resolution of up to 7 bits-measured by comparing the reconstructed waveform with the original input signal. Measured access times for writing/reading to/from the memory registers are of 200 ns. I/O rates via the l6-line-wide I/O bus exceed 10 Msamples/s. Storage time at room temperature is in the 80 to 100 ms range, without accuracy loss.

Cellular neural/nonlinear networks (CNN) are considered for efficient implementation of the most computationally intensive steps of dynamic image coding. Several analogic CNN algorithms are presented for the generation of binary image masks and image decomposition. Measurement results for the first CNN universal chips executing an analogic algorithm for a reconstruction operator are also presented. Based on measured execution times, the viability of the CNN implementation of efficient but computationally expensive compression algorithms such as dynamic image coding is assessed.

Size modification of binary pictures can be mapped onto the CNN array using space variant linear templates. However, if all the parameters have to be set for each cell individually, then one of the CNN's main advantages will be lost in practice, the simple and quick parallel reprogrammability. In this paper, a general methodology is presented to derive the space variant templates of the complete weighting matrix from control pictures applying a simple nonlinear space invariant template. The straightforward design method presumes a modified CNN architecture (multiple input and specific nonlinear voltage-controlled current sources in every cell) and can be extended for a large class of sparse weighting matrices. Following this strategy the diminishment and enlargement process has been investigated using constant cell current and various bias maps in the transformations.

The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 /spl mu/m process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a one-neighborhood with 9 feedback and 9 control coefficients. The cell size is 619 /spl mu/m by 425 /spl mu/m and the simulated speed is between 1 MHz and 10 MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 10/sup 9/ XPS for a single chip operation with an effective area of 0.379 cm/sup 2/ and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.>

The various special features of cellular neural networks are presented. It is stated what has been achieved so far and what future work is still needed in order to obtain a truly universal building block for information processing systems.>