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Daniel Maskit

dblp:92/3346 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 2 · 1 first-authorSystems, architecture and hardware · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia
1 paper
Rendering · 77% Visual content generation and editing · 23%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 56% Parallel and multicore computing · 44%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Rendering
production rendering
0.012003
Production-grade scene translation pipelines · SIGGRAPH 2003
Processor architecture and microarchitecture
multithreading
0.011998
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor · ISCA 1998
Parallel and multicore computing › synchronization
synchronization mechanisms
0.011998
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor · ISCA 1998
Visual content generation and editing
3d content creation
0.012003
Production-grade scene translation pipelines · SIGGRAPH 2003

Methods — techniques the papers use, named apart from their topics

scene graph translation · 0.0simulation · 0.0
YearPublicationVenuePosition
2003 Production-grade scene translation pipelines
abstract
No abstract available.
Daniel Maskit, Chamberlain Fong
SIGGRAPH1
1998 Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
abstract
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, parallelism has been exploited either at the instruction level with a grain-size of a single instruction or by partitioning applications into coarse threads with grain-sizes of thousands of instructions. Fine-grain threads fill the parallelism gap between these extremes by enabling tasks with run lengths as small as 20 cycles. As this fine-grain parallelism is orthogonal to ILP and coarse threads, it complements both methods and provides an opportunity for greater speedup. This paper describes the efficient communication and synchronization mechanisms implemented in the Multi-ALU Processor (MAP) chip, including a thread creation instruction, register communication, and a hardware barrier. These register-based mechanisms provide 10 times faster communication and 60 times faster synchronization than mechanisms that operate via a shared on-chip cache. With a three-processor implementation of the MAP: fine-grain speedups of 1.2-2.1 are demonstrated on a suite of applications.
Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang 0001, Whay Sing Lee
ISCA3
1994 A Message-driven Programming System for Fine-grain Multicomputers
abstract
Abstract This paper describes an experimental message‐driven programming system for fine‐grain multicomputers. The initial target architecture is the J‐machine designed at MIT. This machine combines a unique collection of architectural features that include fine‐grain processes, on‐chip associative memory; and hardware support for process synchronization. The programming system uses these mechanisms via a simple message‐driven process model that blurs the distinction between processes and messages: messages correspond to processes that are executed elsewhere in the network. This model allows code and data to be distributed across the computers in the machine, and is supported at every stage of the program development cycle. The prototype system we have developed includes a basic set of programming tools to support the model; these include a compiler, linker, archiver, loader and microkernel. Although the concepts are language independent, our prototype system is based on GNU‐C.
Daniel Maskit
Softw. Pract. Exp.1