An analysis for a multiprocessor system with a shared bus is given. The analysis applies to application areas where the task to be performed can be partitioned into largely independent subtasks. Each subtask requires cyclic execution on continuous data input. The objective is to determine the processing power of such a system as the number of subtasks or, equivalently, as the number of processors is increased.

This paper introduces a system architecture which allows a high degree of restructuring so that system resources may be tailored to processing requirements. The proposed system organization consists of a large number of byte-slice processors interconnected through a system of busses. Each processor is capable of communicating with every other processor in the system and any number of adjacent processors may be strung together to create a wider arithmetic capability than is possible with a single processor. Processors may be organized into a number of independent teams while processor teams may, in turn, be organized in a hierarchical fashion to allow for concurrent processing. Processor teams may function either in cooperation with or completely independent of other processor teams.