Lung-Jen Lee

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VLDB 2026 Research / reviewers in the wild / expert

dblp:92/3489 · DBLP profile ↗

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5ranked-venue papers

4as first author

0since 2021 · last 2013

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Electronic design automation hardware verification and test	0.1	1	2012	$2^{n}$ Pattern Run-Length for Test Data Compression · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › hardware verification and test test data compression	0.1	1	2012	$2^{n}$ Pattern Run-Length for Test Data Compression · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › hardware verification and test test application time reduction	0.0	1	2012	$2^{n}$ Pattern Run-Length for Test Data Compression · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012

Methods — techniques the papers use, named apart from their topics

run-length encoding · 0.1

Year	Publication	Venue	Position
2013	Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction Lung-Jen Lee	J. Electron. Test.	1
2012	$2^{n}$ Pattern Run-Length for Test Data Compression abstract This paper presents a new pattern run-length compression method whose decompressor is simple and easy to implement. It encodes 2\|n\| runs of compatible or inversely compatible patterns, either inside a single test data segment or across multiple test data segments. Experimental results show that it can achieve an average compression ratio of 67.64% and considerable test application time savings. Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1
2010	Test Data Compression Using Multi-dimensional Pattern Run-length Codes Wang-Dauh Tseng, Lung-Jen Lee	J. Electron. Test.	2
2009	A Multi-dimensional Pattern Run-Length Method for Test Data Compression abstract This paper presents a run-length-based compression method considering dimensions of pattern information. Information such as pattern length and number of pattern runs is encoded to denote the compression status. The decoder is simple and requires very low hardware overhead. Significant improvements are experimentally demonstrated on larger ISCAS'89 benchmarks. Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chen-Lun Lee	Asian Test Symposium	1
2009	Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing abstract Large test data volume and excessive testing power are two strict challenges for VLSI testing. This paper presents a deterministic BIST using multiple LFSRs to generate the low power test set. Experimental results show, the two problems, especially in the reduction of testing power, can be significantly improved with limited hardware overhead. Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chi-Wei Yu	Asian Test Symposium	1