Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. As pinpointed in the last ITRS report and also clearly highlighted in the past years test conference programs, the overall mission of manufacturing test is continuously shifting from its “screening defects” basic and primary objective towards more subtle and secondary goals constituted for example by reliability aspect and yield learning. Just after his retirement, the author examines these new testing opportunity and will try to give directions to all what he missed and failed to do in his research career.

With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture interesting for a yield improvement purpose.

Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR architectures for logic cores to increase SoC yield.

Nanoscaled SRAMs are now becoming more and more prone to device parameter deviations. In this paper, we consider threshold voltage (Vt) deviations in 6T core-cells designed with 90 nm technology. Static faults (transition and read destructive) but also dynamic faults (dynamic read destructive) are obtained as resulting faulty behaviors. Moreover, electrical data show that PVT (process, voltage, temperature) corners that maximize the detection of these faults are quite unconventional. Especially, we show that Vt deviations have their main impact at low voltage while hard defects, such as resistive-open defects in the core-cell, better manifest themselves at high voltage. This study of parameter deviations opens an additional problematic for the test of nanoscaled SRAMS that will be much more severe in deeper technologies (65 nm and 45 nm).

In this paper, we present a diagnosis methodology targeting the whole set of bridging faults leading to either static or dynamic faulty behavior. The adopted diagnosis algorithm resorts only to logic information provided by the tester without requiring a detailed description of the fault models. It is based on an Effect-Cause analysis providing a ranked list of suspects always including the root cause of the observed error. Experimental results on benchmarks ISCAS'89 and ITC '99 show the efficiency of the proposed solution in terms of diagnosis resolution and required computational time.

This paper presents an analysis of the electrical origins of slow write driver faults (SWDFs) (van de Goor et al., 2004) that may affect SRAM write drivers in 65nm technology. This type of fault is the consequence of resistive-open defects in the control part of the write driver. It involves an erroneous write operation when the same write driver performs two successive write operations with opposite data values. In the first part of the paper, we present the SWDF electrical phenomena and their consequences on the SRAM functioning. Next, we show how SWDFs can be sensitized and observed and how a standard March test is able to detect this type of fault

The embedded flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. First, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.15 mum eFlash technology. Next, we propose a study of resistive defect injections in eFlash memories to show the relevance of the proposed simulation model. At the end of the paper, a table summarizes the functional fault models for different resistive defect configurations and experimental set-ups. According to these first results and with additional analysis of actual defects presented in [1] we are then able to enhance existing test solutions for eFlash testing.

In this paper, we present an analysis of resistive-open defects in the sense amplifier of SRAMs designed with the Infineon 65 nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been published in the past. This faulty behavior can be modeled as a dynamic two-cell Incorrect Read Fault (d2cIRF). Such d2cIRF is the consequence of a failure in the sense amplifier which prevents it to perform any read operations. We show that it requires a specific sequence of read operations to be detected. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior. Finally, a possible March test solution is presented to allow the detection of d2cIRFs in all sense amplifiers of an SRAM.

This paper presents DERRIC (Diagnosis of logic ERRors in VLSI Integrated Circuits), a diagnostic tool targeting most of the fault models used in practice today. This tool is intended to be used to diagnose faulty behaviors in nanometric circuits for which the classical stuck-at fault model is far to cover all the realistic failures. The underlying method of DERRIC is based on the Effect-Cause approach which relies on the two following main operations. The first one is based on critical path tracing (CPT) that consists in identifying critical lines in the Circuit Under Test (CUT) which can be the source of observed errors. The second one consists in allocating a set of possible fault models to each critical line, so that root causes of failures can be finally determined. The main advantage of this method is that it does not need to explicitly consider each fault model during the diagnosis process. Experiments on ISCAS'85 and ITC'99 benchmarks show the efficiency of the proposed tool in terms of diagnosis resolution.

The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like Flash. As any kind of memories, embedded Flash (eFlash) can be subjected to complex functional faults that are related to their particular technological process and to their integration density. In this paper, we address a major issue during eFlash testing, namely the test of Address decoder Faults (AFs), which is generally very time consuming with ad-hoc solutions presently used in industry. In the first part of the paper, we show the impact of AFs on the functional behavior of an eFlash. Next, we use an analogy with RAM memory testing to classify AFs with respect to their functional behavior. We then obtain AFs acting either as stuck-at faults or as state coupling faults. In the fourth part of the paper, we propose a concurrent approach for testing AFs acting on either the word line decoder or the bit line decoder. The proposed approach allows using a minimal number of programming operations during test application. Finally, we propose a compaction procedure to further reduce the test time of AFs. As a result, huge reductions in test time can be achieved; experiments on a 4 Mbits eFlash have shown that a test time reduction factor of 34x can be obtained when compared to the global eFlash test flow presently used in industry. An additional important feature of the proposed strategy is that it allows testing 100% of other critical faults in eFlashs (stuck-at, transition and state coupling faults) beside full coverage of AFs.

The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, the authors analyze the impact of a defective tunnel window oxide thickness. The authors show that this defective oxide thickness impacts erase or/and write operations as well as the retention and reliability of the eFlash. The proposed solution to detect such a defective oxide consists in using the voltage disturbance due to the coupling phenomenon existing between bit lines. This particular defective mechanism can be modeled as a coupling fault, especially a state coupling fault. Based on this analysis, the authors propose a test solution that uses two checkerboard patterns; checkerboard pattern (CKB) and its complement (CKBI). The authors show that these two patterns have to be applied by using a parallel programming approach, which allows to increase the coupling phenomenon and thus the voltage disturbance

In this paper, we present an analysis of resistive-open defects in the write driver of SRAMs designed with the Infineon 65nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been experienced in the past. This faulty behavior can be modeled as an un-restored destructive write fault (URDWF). Such URDWF is a consequence of the structural dependencies that exist between the write driver and the sense amplifier, and appears when a specific read operation is performed immediately after a specific write operation. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior and to highlight the difference with a standard un-restored write fault (URWF) model. Next, a possible March test solution is presented to detect URDWF. Finally, a discussion is proposed on the opportunity to include new features in this part of the memory to easily distinguish between faults coming from the write driver (like URDWF) and those coming from other parts of the memory (sense amplifier, core-cells, etc.)

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, the authors propose in this paper to modify an existing test data compression technique so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded intellectual property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 20times reduction in test data volume and 95% test power reduction can be obtained simultaneously

Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Then, we propose a solution based on power-aware assignment of don't care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS'89 and ITC'99 benchmark circuits with the proposed structural-based power-aware X-filling technique. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence length

Non-volatile flash memories are becoming more and more popular for system-on-chip design (SoC). Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. Studies of realistic failure mechanisms and their associated fault models are the first mandatory step before providing efficient and practical new test methods. In this paper, we present an analysis made on actual failures occurring in 2T FLOTOX cells of 0.15mum NOR-based embedded flash structure

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. Recently, we proposed a technique based on clustering and reordering of scan cells that allows to design low power scan chains according to Y. Bonhomme et al. (2003). The main feature of this technique is that power consumption during scan testing is minimized while constraints on scan routing are satisfied. In this paper, we propose a new version of this technique. The clustering process has been modified to allow a better distribution of scan cells in each cluster and hence lead to more important power reductions. Results are provided at the end of the paper to highlight this point and show that scan design constraints (length of scan connections, congestion problems) are still satisfied.

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Power consumption during scan testing is becoming a primary concern. In this paper, we present a novel approach for scan cell ordering which significantly reduces the power consumed during scan testing. The proposed approach is based on the use of a two-step heuristic procedure that can be exploited by any chip layout program during scan flip-flops placement and routing. The proposed approach works for any conventional scan design and offers numerous advantages compared with existing low power scan techniques. Reductions of average and peak power consumption during scan testing are up to 58% and 24% respectively for experimented ISCAS benchmark circuits.

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.

Test power is now a big concern in large system-on-chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores. The proposed low power technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path. The idea is to reduce the clock rate on scan cells during shift operations without increasing the test time. Numerous advantages can be found in applying such a technique.

In this paper, we present a new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique during BIST.

This paper proposes a method to select observation points and flip-flops for partial reset. The method does not target minimum DFT insertion but a maximum improvement on testability. The proposed non-scan approach allows a at-speed testing. Experimental results show that the method achieves 100% fault coverage and 100% fault efficiency for benchmark circuits while requiring less ATPG effort (CPU time) with no scan necessity.

A new BIST TPG design that is comprised of an Adjacency-based TPG plus a conventional pseudo-random TPG (i.e. a LFSR) is presented in this paper. When used to generate test patterns for test-per-clock BIST, it reduces the number of transitions that occur in the CUT and hence decreases the average and peak power consumption during testing. Moreover, the total energy consumption during BIST is also reduced since the test length produced by the mixed TPG is roughly the same as the test length produced by a classical LFSR-based TPG to reach the same fault coverage. Note that this TPG design has been developed to deal with strongly connected circuits with a small number of inputs.

Power consumption of digital systems may increase significantly during testing. In this paper, we propose a novel low power/energy Built-in Self Test (BIST) strategy based on circuit partitioning. The strategy consists of partitioning the original circuit into structural subcircuits so that each subcircuit can be successively tested through different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. The average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the subcircuits is not so far from the test length for the original circuit. The proposed strategy can be applied to either test-per-scan or test-per-clock BIST schemes by slightly modifying conventional TPG structures as illustrated in this paper. Results on ISCAS circuits show that average power reduction of up to 62%, peak power reduction of up to 57%, and energy reduction of up to 82% can be achieved at a very low area cost in terms of area overhead and with almost no penalty on the circuit timing.

We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence generator capable of reproducing the essential features of a set of precomputed deterministic test sequences. We use for this purpose two new models called hidden Markov model with patterns and independence model with patterns. Compared to existing methods, the proposed technique exhibits a very high fault coverage, including performance testing, at the expense of a low silicon area overhead.

In this paper, we propose a novel low power/energy built-in self test (BIST) strategy based on circuit partitioning. The goal of the proposed strategy is to minimize the average power, the peak power and the energy consumption during pseudo-random testing without modifying the fault coverage. The strategy consists in partitioning the original circuit into two structural subcircuits so that each subcircuit can be successively tested through two different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. the average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the two subcircuits is roughly the same as the test length for the original circuit. Results on ISCAS circuits show that average power reduction of up to 72%, peak power reduction of up to 53%, and energy reduction of up to 84% can be achieved.

This paper introduces a set of analytical formulations for 3D modelling of inter-layer capacitances. Efficiency and accuracy are both guaranteed by the process characterization approach. Analytical modelling of interconnect capacitances is then demonstrated to be an helpful alternative to lookup tables or numerical simulations.

This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on the reordering of test vectors of a given test sequence to minimize the average and peak power dissipation during test operation. For this purpose, the proposed technique reduces the internal switching activity by lowering the transition density at circuit inputs. The technique considers combinational or full scan sequential circuits and do not modify the initial fault coverage. Results of experiments show reductions of the switching activity ranging from 11% to 66% during external test application.

During self-test, the switching activity of the circuit under test is significantly increased compared to normal operation and leads to an increased power consumption which often exceeds specified limits. In the first part of this paper, we propose a test vector inhibiting technique which tackles the increased activity during test operation. Next, a mixed solution based on a reseeding scheme and the vector inhibiting technique is proposed to deal with hard-to-test circuits that contain pseudo-random resistant faults. From a general point of view, the goal of these techniques is to minimize the total energy consumption during test and to allow the test at system speed in order to achieve high fault coverage. The effectiveness of the proposed low energy BIST scheme has been validated on a set of benchmarks with respect to hardware overhead and power savings.

This paper presents a new effective BIST scheme that achieves 100% fault coverage with low hardware overhead, and without any mollification of the circuit under test, i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator (e.g. an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very simply and with low silicon area cost, without the need of any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length.

When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the serial shifting procedure. In the literature, different scan modification possibilities have been proposed for applying delay fault oriented deterministic test patterns. Another issue of the delay fault testing problem in scan-based sequential circuits is presented in this paper. The solution combines a BIST structure with the standard scan design.

Minimising the testing costs of boards and MCMs implies to invest in testability analysis in addition to the use of testing standards (IEEE 1149). In this paper, we propose a testability analysis method for boards and MCMs designed at Dassault Electronique. The actual prototype realised according to this new methodology aims at helping testability expert.

With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this papel; we propose a post-mapping technique that can reduce the power dissipation by peeorming gate resizing.This technique consists of replacing some gates of the circuit with devices in a complete cell library having smaller area and, therefore, smaller gate capacitance with lower power consumption.The slack time of each gate in the circuit is first computed to determine the set of gates that can be down-sized.A global optimization procedure based on integer linear programming and the simplex method is then applied to determine the best overall gate resizing solution.Experimental results on benchmark circuits have shown a power reduction in the rangefrom 2.8 to 27.9 % compared to circuits without resizing.The most relevant features of our technique are that it is applicable to large digital circuits and gives an optimal resizing solution in a short computation time (no more than 15.8 seconds).

This paper presents a new approach for designing test sequences to be generated on-chip. The proposed technique is based on machine learning, and provides a way to generate efficient patterns to be used during BIST test pattern generation. The main idea is that test patterns detecting random pattern resistant faults are not embedded in a pseudo-random sequence as in existing techniques, but rather are used to produce relevant features allowing to generate directed random test patterns that detect random pattern resistant faults as well as easy-to-test faults. A BIST implementation that uses a classical LFSR plus a small amount of mapping logic is also proposed. Results are shown for benchmark circuits which indicate that our technique can reduce the weighted or pseudo-random test length required for a particular fault coverage. Other results are given to show the possible trade off between hardware overhead and test sequence length. An encouraging point is that results presented in this paper although they are comparable with those of existing mixed-mode techniques, have been obtained with a machine learning tool not specifically developed for BIST generation and therefore may significantly be improved.

As delay testing using external testers requires expensive equipment, built-in self-test (BIST) is an alternative technique that can significantly reduce the test cost. In this paper, a BIST test pattern generator (TPG) design for the detection of delay faults is proposed. This TPG design produces test sequences having exactly the same robust delay fault coverage as single input change (SIC) test sequences obtained with the most efficient TPGs proposed before in the literature, but with a reduced test length and less area overhead. This reduction of the test length and area overhead is obtained by determining compatible inputs of the circuit under test (CUT), i.e. inputs that can be switch simultaneously without altering the robust test coverage.

This paper presents a GA-based technique to generate diagnostic-oriented delay tests for logic circuits. The aim is to produce a test sequence for a given circuit such that any couple of non-equivalent delay faults is distinguished by at least one rest pair belonging to the test sequence. For this purpose, we decided to preferably use a simulation-based approach with a directed search mechanism rather than developing a new deterministic ATPG. An appropriate fitness function that ranks population members according to their diagnostic capabilities has been defined, and genetic operators allowing a population to evolve during successive generations are presented. In order to have a diagnostic program providing near-optimal solutions, we combined the GA-based technique proposed in this paper with an existing post test diagnostic method for delay faults. Experimental results show that the genetic approach is effective for solving our diagnostic test generation problem, and point out the fact that the GA performs very well in comparison to a random test method.

Importance of delay testing is growing especially for high speed circuits. As delay testing using automatic test equipment is expensive, built-in self-test is an alternative technique that can significantly reduce the cost of delay testing. In this paper a new test pattern generation method for the detection of delay faults is proposed. It can be seen as a directed random generation technique, and uses some original concepts from machine learning to generate delay fault detecting test pairs. First, a set of random test vectors is generated. Next, a learning tool working on those vectors provides relevant features of delay fault detecting test pairs. Finally, a set of new test vectors that are consistent with those features is generated. A comparison with other test generation techniques has been done on several circuits, and has shown the efficiency of our solution in terms of test sequence length and delay fault coverage.

The majority of design for testability (DFT) methods for sequential circuits are based on scan designs (complete or partial). Nevertheless, with these methods the test application time remains often prohibitive due to the long shift operation to enter the test vector into the scan register. In this paper, we present a DFT method which modifies the circuit in such a way that, during the test operation, several more easily testable configurations are emulated. Different implementations are proposed for these test configurations that are shown to be useful to improve either the controllability or the observability. The efficiency of the method is evaluated in terms of fault coverage, number of modified flip-flops and test application time, using ISCAS89 benchmarks.

High level synthesis (HLS) is defined as a topdown translation from the behavioral domain to the structural domain where the circuit is represented by a set of connected storage elements and functional units for the datapath and a logic level specification of the corresponding control unit. Testing is a bottom up approach process aiming at detecting realistic faults. Realistic faults depend on the physical domain, the technology process data and on the geometry of inner structures (inductive fault analysis). HLS cannot solve all the testing problems, but it may facilitate solutions by providing easier control or observation of internal units. Furthermore, the so produced designs exhibit less area and speed penalties than those obtained by applying a posteriori DFT techniques on synthetized gate level descriptions.

The goal of fault diagnosis is to identify the causes of device failures. Different techniques have been proposed for stuck-at fault diagnosis in combinational as well as sequential circuits. On the other side, diagnosis of delay faults has received attention for the first category of circuits, but not for synchronous sequential circuits. So, this paper concerns delay fault diagnosis for non-scan circuits. A preliminary version of the proposed method is first given. New concepts for allowing path tracing in the proposed diagnosis process (identification of self-masking) are also presented. As the method is based on path tracing through the sequential circuit, gate delay faults as well as path delay faults are considered and may be located in a faulty machine. Results of experiments on ISCAS-89 benchmark circuits are finally discussed.

Existing methodologies for determining delay fault coverages or for building up a delay fault dictionary are sometimes accurate, but rarely fast and easy to implement. Therefore, with the aim of removing these deficiencies, a new and more efficient fault simulation strategy for gate delay faults in combinational or scan-based circuits is presented. This method is based on a critical path tracing algorithm, thus avoiding the explicit simulation of each delay fault in the circuit. The novelty of the solution proposed to compute the detection threshold of a detectable delay fault increases the interest of the method, although it is computed approximately. Simulation results obtained for the ISCAS85 combinational benchmark circuits show the efficiency of the proposed method.>

Autonomous linear finite state machines with both complemented and uncomplemented register outputs (mixed-output ALFSMs) have been investigated for their use as deterministic and pseudo-random test vector generators in a BIST scheme. The authors describe a method for deriving the feedback connections of the mixed-output ALFSM given a deterministic sequence of n n-bit wide test vectors. They also show that the state graph structure is preserved thus enabling the generation of maximum-length sequences if the characteristic polynomial of the connectivity matrix is primitive. An example is given to illustrate the synthesis method of a mixed-output ALFSM based test vector generator. A better solution is obtained compared to conventional uncomplemented output ALFSM.>

Self-checking approaches developed so far deal with a gate level representation of logical circuits. They do not account for constraints which may result from an implementation by integrated circuits. This paper is concerned with such practical problems and their respective significance.

Modeling of systems featuring hardware and software faults is studied as a means of evaluating the availability and reliability characteristics. The case of a nonredundant computer is studied and it is shown that the unavailability presents an overshoot with respect to its asymptotic value whose height and length are functions of the failure rates associated with the different design errors. Fault-tolerant systems are studied that include protective redundancies both at the hardware level and at the software level; the importance of homogeneous solutions on both levels is shown.