GIRAF is a General purpose In-storage Resistive Associative Framework based on resistive content addressable memory (RCAM), which functions simultaneously as a storage and a massively parallel associative processor. GIRAF alleviates the bandwidth wall by connecting every memory bit to processing transistors and keeping computing inside the storage arrays, thus implementing deep in-data, rather than near-data, processing. We show that GIRAF outperformed a reference computer architecture with a bandwidth-limited external storage access on a variety of data-intensive workloads. The performance of GIRAF Dot Product and Sparse Matrix-Vector multiplication exceeds the attainable performance of a reference architecture by 1200 × and 130 ×, respectively.

Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory failures are 1) wear-leveling, to evenly distribute the writes across the entire memory, and 2) fault tolerance, to correct memory cell failures. However, one of the main open challenges in extending the lifetime of existing resistive memories is to make both techniques work together seamlessly and efficiently. To address this challenge, we propose WoLFRaM, a new mechanism that combines both wear-leveling and fault tolerance techniques at low cost by using a programmable resistive address decoder (PRAD). The key idea of WoLFRaM is to use PRAD for implementing 1) a new efficient wear-leveling mechanism that remaps write accesses to random physical locations on the fly, and 2) a new effiCient fault tolerance mechanism that recovers from faults by remapping failed memory blocks to available physical locations. Our evaluations show that, for a Phase Change Memory (PCM) based system with cell endurance of 108writes, WoLFRaM increases the memory lifetime by 68% compared to a baseline that implements the best state-of-the-art wear-leveling and fault correction mechanisms. WoLFRaM's average / worst-case performance and energy overheads are 0.51% /3.8% and 0.47% /2.1% respectively.

Genome sequences contain hundreds of millions of DNA base pairs. Finding the degree of similarity between two genomes requires executing a compute-intensive dynamic programming algorithm, such as Smith-Waterman. Traditional von Neumann architectures have limited parallelism and cannot provide an efficient solution for large-scale genomic data. Approximate heuristic methods (e.g. BLAST) are commonly used. However, they are suboptimal and still compute-intensive.

Genome sequences contain hundreds of millions of DNA base pairs. Finding the degree of similarity between two genomes requires executing a compute-intensive dynamic programming algorithm, such as Smith-Waterman. Traditional von Neumann architectures have limited parallelism and cannot provide an efficient solution for large-scale genomic data. Approximate heuristic methods (e.g. BLAST) are commonly used. However, they are suboptimal and still compute-intensive. In this work, we present BioSEAL, a biological sequence alignment accelerator. BioSEAL is a massively parallel non-von Neumann processing-in-memory architecture for large-scale DNA and protein sequence alignment. BioSEAL is based on resistive content addressable memory, capable of energy-efficient and high-performance associative processing. We present an associative processing algorithm for entire database sequence alignment on BioSEAL and compare its performance and power consumption with state-of-art solutions. We show that BioSEAL can achieve up to 57x speedup and 156x better energy efficiency, compared with existing solutions for genome sequence alignment and protein sequence database search.

GIRAF is an in-storage architecture and algorithm framework based on Resistive Content Addressable Memory (RCAM). GIRAF functions simultaneously as a storage and a massively parallel associative processor. GIRAF alleviates the bandwidth wall by connecting every memory bit to processing transistors and keeping computing inside the storage arrays, thus implementing in-data, rather than near-data, processing. We show that GIRAF outperforms a reference computer architecture with a bandwidth-limited external storage access on a variety of data intensive workloads. The performance of GIRAF Euclidean distance, dot product and histogram implementation, exceeds the attainable performance of a reference architecture by up to four orders of magnitude, depending on the dataset size. The performance of GIRAF SpMV exceeds the attainable performance of such reference architecture by more than two orders of magnitude.

Proprietary cryptographic algorithms or protection schemes often constitute part of the security solution in electronic devices. Hence, these devices are prone to reverse engineering attacks that may reveal the details of these algorithms. We propose a novel non-invasive method of reverse engineering of digital integrated circuits that exploits the scan chains originally inserted into the device for production test automation. The scan chains unfold the sequential logic of the device to form a combinational function. The device's functionality is then exposed by examining this function. The resulting function is too large for direct learning, so we developed heuristic learning algorithms that exploit common properties of digital circuits, in particular limited transitive fan-in of combinational logic and sub-circuit sharing properties. \deleted{We discuss the complexity model and applicability of the algorithms. }With these algorithms we show fast reconstruction of an AES cryptographic accelerator. The algorithm used for the AES is scalable, making it applicable to much larger circuits.

In the growing heterogeneous Internet of Things market, which embraces a plurality of vendors and service providers, IP protection plays a central role. This paper proposes a process for the detection of IP theft in VLSI devices that exploits the internal test scan chains, designed for production test automation. The scan chains supply direct access to the internal registers in the device, enabling combinational analysis of the device logic. By using Boolean function learning methods, the learner creates a partial dependence graph of the internal flip-flops. The graph is further partitioned using the shared nearest neighbors graph clustering method, and individual blocks of combinational logic are isolated. These blocks can be matched with known building blocks that compose the original function. This enables reconstruction of the function implementation to the level of pipeline structure. The IP owner can compare the resulting structure with his own implementation to confirm whether an IP violation has occurred. We demonstrate the power of the presented approach with a test case of an open source Bitcoin SHA-256 accelerator, containing more than 80 000 registers. With the presented method, we discover the microarchitecture of the module, locate all the main components of the SHA-256 algorithm, and learn the module's flow control. In addition to the direct recognition of the IP content, we also demonstrate a combination of reverse engineering and watermark methods. We define a new watermark structure-pipeline-associated watermark (PAW), combined with pipeline stages that can be detected with the scan-based reverse engineering method.

GP-SIMD, a novel hybrid general-purpose SIMD architecture, addresses the challenge of data synchronization by in-memory computing, through combining data storage and massive parallel processing. In this article, we explore a resistive implementation of the GP-SIMD architecture. In resistive GP-SIMD, a novel resistive row and column addressable 4F 2 crossbar is utilized, replacing the modified CMOS 190F 2 SRAM storage previously proposed for GP-SIMD architecture. The use of the resistive crossbar allows scaling the GP-SIMD from few millions to few hundred millions of processing units on a single silicon die. The performance, power consumption and power efficiency of a resistive GP-SIMD are compared with the CMOS version. We find that PiM architectures and, specifically, GP-SIMD benefit more than other many-core architectures from using resistive memory. A framework for in-place arithmetic operation on a single multivalued resistive cell is explored, demonstrating a potential to become a building block for next-generation PiM architectures.

This work studies the influence of temperature on performance and scalability of 3D Chip Multiprocessors (CMP) from Amdahl's law perspective. We find that 3D CMP may reach its thermal limit before reaching its maximum power. We show that a high level of parallelism may lead to high peak temperatures even in small scale 3D CMPs, thus limiting 3D CMP scalability and calling for different, in-memory computing architectures.

This study presents a computer architecture, where a last-level cache and a SIMD accelerator are replaced by an associative processor. Associative processor combines data storage and data processing, and functions as a massively parallel SIMD processor and a memory at the same time. An analytic performance model of this computer architecture is introduced. Comparative analysis supported by cycle-accurate simulation and emulation shows that this architecture may outperform a conventional computer architecture comprising a SIMD coprocessor and a shared last-level cache while consuming less power.

Sparse matrix multiplication is an important component of linear algebra computations. Implementing sparse matrix multiplication on an associative processor (AP) enables high level of parallelism, where a row of one matrix is multiplied in parallel with the entire second matrix, and where the execution time of vector dot product does not depend on the vector size. Four sparse matrix multiplication algorithms are explored in this paper, combining AP and baseline CPU processing to various levels. They are evaluated by simulation on a large set of sparse matrices. The computational complexity of sparse matrix multiplication on AP is shown to be an O(nnz) where nnz is the number of nonzero elements. The AP is found to be especially efficient in binary sparse matrix multiplication. AP outperforms conventional solutions in power efficiency.

System-on-a-chip designs typically employ multiple clock domains to interface several externally clocked circuits operating at different frequencies and to reduce power and area by breaking large clock trees into multiple small ones. The principal challenge of such globally asynchronous locally synchronous architectures is the need to reliably communicate between the different clock domains. To achieve high reliability margins in high-frequency designs implemented in modern process technologies, multistage synchronizers are often used. In this paper, we develop analytical formulas to calculate the probability of failure and the number of stages to use in such synchronizers. We compare our model with those reported in previous publications and show that most existing models underestimate mean time between failures (MTBF). Our model calculates an MTBF lower bound with significantly smaller margins. The concept of an effective resolution time constant for multistage synchronizers is introduced and the important effects of clock duty cycle and process variability are addressed. These process variability effects can be minimized by use of simple design rules for the synchronizer. For safety-critical applications, calculation of the probability of a failure-free lifetime for all products in a production run is developed and a simple lower bound is derived.

Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to the entire integrated circuit, while others can be adjusted for each individual synchronizer in the design. The following guidelines are provided to improve synchronizers: avoiding scan and reset, selecting minimum size flip-flop cells, minimizing routing, reducing jitter in coherent clock domain crossings, opting for high-performance process flavor and minimumVTH, overprovisioning to account for variations, maximizing supply voltage, and manipulating clock duty cycle.

Synchronizers play a key role in multiclock domains systems on chip and their performance is usually measured by the mean-time between failures (MTBF) of the system. Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling for library flip-flop circuits in 65 nm and below. This degradation of parameters becomes critical when the system is operated under extreme supply voltage and temperature conditions. In this paper, we study the behavior of synchronizers in a broad range of supply voltage and temperature conditions. A new model for the metastability time constant (τ), the metastability window (TW), and MTBF is presented. We show a detailed comparison of model, measurements, and simulations for different technology nodes and discuss implications for modern synchronization systems. We propose design guidelines that account for supply voltage and temperature variations and determine the correct number of synchronizer stages required for target MTBF.

Modern superscalar CPUs contain large complex structures and diverse execution units, consuming wide dynamic power range. Building a power delivery network for the worst-case power consumption is not energy efficient and often is impossible to fit in small systems. Instantaneous power excursions can cause voltage droops. Power management algorithms are too slow to respond to instantaneous events. In this article, we propose a novel compiler-directed framework to address this problem. The framework is validated on a 4th Generation Intel® Core™ processor and with simulator on output trace. Up to 16% performance speedup is measured over baseline for the SPEC CPU2006 benchmarks.

GP-SIMD, a novel hybrid general-purpose SIMD computer architecture, resolves the issue of data synchronization by in-memory computing through combining data storage and massively parallel processing. GP-SIMD employs a two-dimensional access memory with modified SRAM storage cells and a bit-serial processing unit per each memory row. An analytic performance model of the GP-SIMD architecture is presented, comparing it to associative processor and to conventional SIMD architectures. Cycle-accurate simulation of four workloads supports the analytical comparison. Assuming a moderate die area, GP-SIMD architecture outperforms both the associative processor and conventional SIMD coprocessor architectures by almost an order of magnitude while consuming less power.

Network-on-Chip (NoC) has emerged as a key architecture component that determines the overall performance, power, and area (PPA) of a contemporary System-on-Chip (SoC) device. The PPA characteristics of NoC are influenced by a wide range of issues, including semi-conductor technology (process node and corner, 2D/3D integration), circuit technology (synchronous, asynchronous), SoC architecture and use-case (number of IP blocks, general purpose or domain specific workload, frequency requirements, voltage, and clock domains), network topology (homogeneous, heterogeneous), routing strategy (deterministic, adaptive), router architecture and features (arity, virtual channels, Quality-of-Service, or QoS), and test architecture. Consequently, research in NoC design covers a wide gamut of topics. This special issue presents the latest advancements in NoC design and optimization.

Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and below. Degradation of parameters can be even worse if the system is operated at extreme supply voltages and temperature conditions. In this work we study the behavior of synchronizers in a broad range of supply voltage and temperature corners. A digital on-chip measurement system is presented that helps to characterize synchronizers in future technologies and a new calibrating system is shown that accounts for changes in delay values due to supply voltage and temperature changes. We present a detailed comparison of measurements and simulations for a fabricated 65nm bulk CMOS circuit and discuss implications of the measurements for synchronization systems in 65nm and beyond. We propose an adaptive self-calibrating synchronizer to account for supply voltage, temperature, global process variations and DVFS.

The internet is rapidly becoming a major consumer of electricity with measurable economic and environmental impact. DVFS is employed in processors for balancing performance and power consumption. We apply DVFS to network controllers to reduce unnecessary power dissipation in networks. When receive and transmit buffers are relatively empty, energy is saved by lowering the packet processing rate. A simulation environment was devel-oped to assess the energy savings achievable with this approach. Simulations show an average energy savings of 29% across vari-ous traffic loads and 19% across various congestion levels.

Clock distribution networks are an essential element of a synchronous digital circuit, a significant power consumer and highly sensitive to process, voltage, and temperature variations. Mesh- and crosslink-based topologies reliably compensate for skew variations in these networks, albeit with a significant increase in dissipated power as compared to variation-sensitive low power clock trees. Existing crosslink-based methods, however, only address skew from an algorithmic perspective at the network topology level. Guidelines for inserting crosslinks within a buffered low power clock tree are provided in this paper. Physical constraints, such as the size of the crosslink and exact location between the driving and load buffers, are analytically described. Metrics to determine the most energy efficient non-tree topology are provided based on closed-form expressions, and verified with simulation.

Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm circuits and beyond. An on-chip metastability measurement circuit was fabricated in a 65nm 1.1V bulk CMOS. A fully digital on-chip measurement system is presented here that helps to characterize synchronizers in future technologies. Different types of synchronizers were measured and compared. The standard library FF is demonstrated to have lower tau value than various feedback flip-flops.

Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. However, these networks incur an increase in dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce skew variations rather than skew, and prioritize the algorithm for critical timing paths, since these paths are more sensitive to skew variations. The algorithm has been implemented for a standard 65 nm cell library using standard EDA tools, and has been tested on several benchmark circuits. As compared to other methods, experimental results show a 37% average reduction in metal consumption and 39% average reduction in power dissipation, while insignificantly increasing the maximum skew.

Providing highly flexible connectivity is a major architectural challenge for hardware implementation of reconfigurable neural networks. We perform an analytical evaluation and comparison of different configurable interconnect architectures (mesh NoC, tree, shared bus and point-to-point) emulating variants of two neural network topologies (having full and random exponential configurable connectivity). We derive analytical expressions and asymptotic limits for performance (in terms of bandwidth) and cost (in terms of area and power) of the interconnect architectures considering three communication methods (unicast, multicast and broadcast). It is shown that multicast mesh NoC provides the highest performance/cost ratio and consequently it is the most suitable interconnect architecture for configurable neural network implementation. Simulation results successfully validate the analytical models and the asymptotic behavior of the network as a function of its size.

Network-on-Chip (NoC) links consume a significant fraction of the total NoC power. We present Selective Packet Interleaving (SPI), a flit transmission scheme that reduces power consumption in NoC links. SPI decreases the number of bit transitions in the links by exploiting the multiplicity of virtual channels in a NoC router. SPI multiplexes flits to the router's output link so as to minimize the number of bit transitions from the previously transmitted flit. Analysis and simulations demonstrate a reduction of up to 55% in the number of bit transitions and up to 40% savings in power consumed on the link. SPI benefits grow with the number of virtual channels. SPI works better for links with a small number of bits in parallel. While SPI compares favorably against bus inversion, combining both schemes helps to further reduce bit transitions.

An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the differential level encoded dual-rail (LEDR) two-phase asynchronous protocol, avoiding per-bit handshake and eliminating per-bit synchronization, in contrast with synchronous serial links that rely on complex clock recovery. Novel low-power current signaling driver and receiver circuits are presented, enabling high-speed communication at a very low voltage swing over long wires. In contrast, previous methods employed voltage sensing, resulting in higher swing, higher dynamic power, shorter wires or slower operation. The asynchronous current mode driver is designed to support varying data rates, and it eliminates the need for balanced codes and busy toggling that prevent deep discharge. The data cycle time of the link is equal to a single gate delay, enabling 67 Gb/s throughput in 65-nm technology. Wave-pipelining is employed also by the asynchronous SERDES circuits, to enable such high speed operation. The link was SPICE simulated for 65-nm technology, using wire models obtained by a 3-D EM solver. The link incurs lower power and area relative to synchronous and asynchronous bit-parallel communications, and these relative benefits also scale with technology.

The unified logical effort (ULE) model for delay evaluation and minimization in paths composed of CMOS logic gates and resistive wires is presented. The method provides conditions for timing optimization while overcoming the limitations of standard logical effort (LE) in the presence of interconnects. The condition for optimal gate sizing in a logic path with long wires is also presented. This condition is achieved when the delay component due to the gate input capacitance is equal to the delay component due to the effective output resistance of the gate. The ULE delay model unifies the problems of gate sizing and repeater insertion: In the case of negligible interconnect, the ULE method converges to standard LE optimization, yielding tapered gate sizes. In the case of long wires, the solution converges toward uniform sizing of gates and repeaters. The technique is applied to various types of logic paths to demonstrate the influence of wire length, gate type, and technology.

In the above titled paper (ibid., vol. 18, no. 5, pp. 689-696, May 10), the formula and the caption in Fig. 3 appeared incorrectly. The correct figure is presented here along with an explanation.

Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutions significantly increase the dissipated power, whereas existing link based methods only address skew caused by variations and do not consider power consumption. The power dissipated by the inserted crosslinks within a buffered clock tree is investigated in this paper, and is shown to be a strong function of the resistance and capacitance of the crosslink. A crosslink may be power efficient despite the presence of short-circuit currents caused by multiple drivers in a non-tree clock network. The power characteristics of crosslink size and placement are also discussed, showing that the crosslink is best placed as close as possible to the target leaves of the tree. Crosslink insertion as both an alternative and complement to buffer sizing for low power skew reduction is also considered.

The Capacity Allocation Paradox (CAP) destabilizes a stable small-buffer network when a link capacity is increased. CAP is demonstrated in a basic 2 times 1 network topology. We show that it applies to fluid, wormhole and packet-switched networks, and prove that it applies to various scheduling algorithms such as fixed-priority, round-robin and exhaustive round-robin. Their capacity regions are modeled and surprising phenomena are described. For instance, once increasing a link capacity destabilizes a stable network, increasing it further to infinity might never restore stability. Further, we exhibit networks with arbitrarily tight link-capacity stability regions, in which any small deviation from an optimal link capacity might make the network unstable. Finally, we suggest ways to mitigate CAP, e.g. by using GPS scheduling.

Power and thermal are major constraints for delivering compute performance in high-end CPU and are expected to be so in the future. CMP is becoming important by delivering more compute performance within the power constraints. Dynamic Voltage and Frequency Scaling (DVFS) has been studied in past work as a mean to increase save power and improving the overall processor's performance while meeting the total power and/or thermal constraints. For such systems, power delivery limitations are becoming a significant practical design consideration, unfortunately this aspect of the design was almost ignored by many research works. This paper explores the various possible topologies to build a high end multi-core CPU and the available policies that maximize performance within the set of physical limitations. It evaluates single and multiple voltage and frequency domains and introduces a new clustered topology, grouping several cores together. A hybrid model, using measurements of a real CPU, cycle accurate simulator and an analytical model is introduced. The results presented indicate that considering power delivery limitations diverts the conclusions when such limitations are ignored. This paper shows that a single power domain topology performs up to 30% better than multiple power domains on light-threaded workload. In the fully threaded application the results divert. Clustered topology performs well for any number of threads.

Chip-multi-processor (CMP) utilize multiple energy-efficient processing elements (PEs) to deliver high performance while reducing energy-consumption. Dynamic frequency-Voltage Scaling (DVS) balances performance and energy consumption by varying PEs' frequency-voltageworkpointsto save energy while meeting performance requirements. We consider multi-task CMP applications with unknown workloads, and dynamically set workpoints to minimize . Heuristic policies for serial/parallel task-graphs are investigated. We compare these policies to a theoretical bound and show that they achieve good results with low complexity. In most cases the simplest policy, which usually assigns constant workpoints, is also the most cost-effective one.

The majority of current network on chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unrealistic due to variations in module sizes and shapes, and is not suitable for application-specific NoCs. Consequently, simplistic routing techniques such as XY routing are inadequate, raising the need for low cost alternatives which can work in irregular mesh networks. In this paper we present a novel technique for reducing the total hardware cost of routing tables for both source and distributed routing approaches. The proposed technique is based on applying a fixed routing function combined with minimal deviation tables that are used only when the routing decisions for a given destination deviate from the predefined routing function. We apply this methodology to compare three hardware efficient routing methods for irregular mesh topology NoCs. For each method, we develop path selection algorithms that minimize the overall cost of routing tables. Finally, we demonstrate by simulations on random and specific real application network instances a significant cost saving compared to standard solutions, and examine the scaling of cost savings with growing NoC size

The paper introduces network-on-chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance chip multi processors (CMPs). We address previously proposed CMP architectures based on non uniform cache architecture (NUCA) over NoC, analyze basic memory transactions and translate them into a set of network transactions. We first show how a simple, generic NoC which is equipped with needed module interface functionalities can provide infrastructure for the coherent access of both static and dynamic NUCA. Then we show how several low cost mechanisms incorporated into such a vanilla NoC can facilitate CMP and boost performance of a cache coherent NUCA CMP. The basic mechanism is based on priority support embedded in the NoC, which differentiates between short control signals and long data messages to achieve a major reduction in cache access delay. The low cost priority-based NoC is extremely useful for increasing performance of almost any other CMP transaction. Priority-based NoC along with the discussed NoC interfaces are evaluated in detail using CMP-NoC simulations across several SPLASH-2 benchmarks and static Web content serving benchmarks showing substantial L2 cache access delay reduction and overall program speedup

An asynchronous router for quality-of service NoC is presented. It combines multiple service levels (SL) with multiple equal-priority virtual channels (VC) within each level. The VCs are assigned dynamically per each link A different number of VCs may be assigned to each SL and per each link The router employs fast arbitration schemes to minimize latency

Network on chip (NoC) may be the primary interconnect mechanism for future systems-on-chip (SoC). Real-life SoCs typically include hot-modules such as DRAM controller or floating point unit, which are bandwidth limited and in high demand by other units. In this paper we demonstrate that the mere existence of one or more hot-modules in a wormhole-based NoC dramatically reduces network efficiency and causes an unfair allocation of system resources. We demonstrate that a single hot-module destroys the performance of the entire SoC, even if network resources are over-provisioned. In order to resolve the hot-module effect, we introduce a novel low-cost credit based distributed access regulation technique that fairly allocates access rights to the hot-module. Unlike other methods, this technique directly addresses the root cause of network buffer congestion phenomena. Using simulation, we show the effectiveness of the suggested mechanism in various NoC scenarios

Spiking neural network (NN) architecture that uses Hebbian learning and reinforcement-learning schemes for adapting the synaptic weights is implemented in silicon and performs dynamic optimization according to hemodynamic sensor for a cardiac resynchronization therapy (CRT) device. The spiking NN architecture dynamically changes the atrioventricular (AV) delay and interventricular (VV) interval parameters according to the information provided by the intracardiac electrograms (IEGMs) and hemodynamic sensors. The spiking NN coprocessor performs the adaptive part and is controlled by a deterministic algorithm master controller. The simulated cardiac output obtained with the adaptive CRT device is 30% higher than with a nonadaptive CRT device and is likely to provide improvement in the quality of life for patients with congestive heart failure. The spiking NN architecture shows synaptic plasticity acquired during the learning process. The synaptic plasticity is manifested by a dynamic learning rate parameter that correlates patterns of hemodynamic sensor with the system outputs, i.e., the optimal AV and VV pacing intervals.

This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under quality-of-service timing constraints. First, we introduce a novel analytical delay model for virtual channeled wormhole networks with non-uniform link capacities that eliminates costly simulations at the inner-loop of the optimization process. Second, we present an efficient capacity allocation algorithm that assigns link capacities such that packet delays requirements for each flow are satisfied. We demonstrate the benefit of capacity allocation for a typical system on chip, where the traffic is heterogeneous and delay requirements may largely vary, in comparison with the standard approach which assumes uniform-capacity links

Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using a timed signal transition graph (STG) approach. In some cases, the problem can be solved by extracting all the delays and verifying whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Three different LDL ports are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner

In battery-operated portable or implantable digital devices, where battery life needs to be maximized, it is necessary to minimize not only power consumption but also energy dissipation. Typical energy optimization measures include voltage reduction and operating at the slowest possible speed. We employ additional methods, including hybrid asynchronous dynamic design to enable operating over a wide range of battery voltage, aggregating large combinational logic blocks, and transistor sizing and reordering. We demonstrate the methods on simple adders, and discuss extension to other circuits. Three novel adders are proposed and analyzed: a 2-bit pass transistor logic (PTL) adder and two dynamic 2-bit adders. Circuit simulations on a 0.18-mum process at low voltage show that leakage energy is below 1%. The proposed adders achieve up to 40% energy savings relative to previously published results, while also operating faster

Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area.

A novel methodology and algorithm for the design of large low-power asynchronous systems are described. The system is synthesized by a commercial tool as a synchronous circuit, and subsequently converted into an asynchronous one. The conversion algorithm consists of extracting input and output sets, replacing the storage elements, identifying fork and join sets, and constructing request and acknowledge networks. A DLAP (doubly latched asynchronous pipeline) architecture is employed. The resulting asynchronous circuit can adapt its effective operating frequency to the supply voltage, facilitating flexible and efficient power management. The algorithm has been validated on several circuits.

Novel gate-diffusion input (GDI) circuits are applied to asynchronous design. A variety of GDI implementations are compared with typical CMOS asynchronous circuits. Dynamic GDI state holding elements are 2/spl times/ smaller than CMOS C-elements, 30% faster, and consume 85% less power, but certain CMOS elements are preferred when static storage is called for. A GDI bundled controller outperforms CMOS on all accounts, having 1/3 the delay and requiring less than half the area while consuming the same power. A combination CMOS-GDI circuit provides the optimal solution for qDI combinational logic, saving 1/3 the power, half the area, and 10% in delay relative to a CMOS implementation. GDI circuits also provide some measure of enhanced hazard tolerance.

System-on-chip (SoC) design depends heavily on effective reuse of semiconductor intellectual property (IP). Clock distribution has become a problem for integrating IP cores into a single synchronous SoC, because of different clock delays in the IP cores. We propose an on-chip clock-tuning circuit, which enhances design flexibility. Programmable delays are inserted in the clock distribution network, such that clock alignment and synchronization are achieved. Design iterations are eliminated with the use of the tuning circuit, saving design effort, and cost. The method is also applicable to compensating for unbalanced clock trees. Hierarchical clock tuning can be implemented and can take advantage of the hierarchical structure of the SoC. Skew analysis has shown that the added programming unit outperforms other clock design options. The method was implemented in a commercial chip, and demonstrated good functionality with high productivity of the design flow.

Relative timing (RT) is introduced as a method for asynchronous design. Timing requirements of a circuit are made explicit using relative timing. Timing can be directly added, removed, and optimized using this style. RT synthesis and verification are demonstrated on three example circuits, facilitating transformations from speed-independent circuits to burst-mode and pulse-mode circuits. Relative timing enables improved performance, area, power, and functional testability of up to a factor of 3/spl times/ in all three cases. This method is the foundation of optimized timed circuit designs used in an industrial test chip, and may be formalized and automated.

Turbo codes achieve performance near the Shannon limit. Standard sequential VLSI implementation of turbo decoding requires large memory and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for turbo decoding is described, comprising multiple SISO (soft-in soft-out) elements, operating jointly on one turbo coded block, and a new parallel interleaver. Latency is reduced up to twenty times and throughput for large blocks is increased up to five-fold relative to sequential decoders, using the same area of silicon, and achieving the same coding gain. The parallel architecture scales favourably - latency and throughput improve with growing block size and chip area.

This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 instruction length decoding and steering unit called RAPPID ("revolving asynchronous Pentium processor instruction decoder") that was fabricated and tested successfully. Silicon results show significant advantages-in particular, performance of 2.5-4.5 instructions per nS-with manageable risks using this design technology. RAPPID achieves three times faster performance and half the latency dissipating only half the power and requiring a minor area penalty as a comparable 400 MHz clocked circuit. Relative timing is based on user-defined and automatically extracted relative timing assumptions between signal transitions in a circuit and its environment. It supports the specification, synthesis, and verification of high-performance asynchronous circuits, such as pulse-mode circuits, that can be derived from an initial speed-independent specification. Relative Timing presents a "middle-ground" between clocked and asynchronous circuits, and is a fertile area for CAD development. We discuss possible directions for future CAD development.

Delay variations are typically accounted for by increasing cycle time margins. Adaptive synchronization eliminates this on inter-modular interfaces in very large, high performance chips. The chip is divided into multiple smaller synchronous modules. Multi-synchronous hierarchical clocking provides the same frequency to all modules, but does not maintain any particular phase. Adaptive synchronizers adapt to the time-varying inter-modular clock and data phases, and out-perform conventional synchronizers.

[email protected] Kin is an asynchronous processor architecture designed for future technologies enabling one or more billion transistors per chip and extremely fast processing (e.g., as predicted for 2012). This huge resource is exploited for aggressive avid execution, where a large number of instructions (hundreds per cycle) are prefetched and executed speculatively, in order to reduce the penalty of stalls due to branch mispredictions and dependencies, and to yield a very aggressive rate of successfully completed instructions (tens of instructions every cycle). Unneeded instructions are removed efficiently and nonpreemptively, under control of apruning mechanism. A multi-ported, wide bandwidth decoded instruction cache, wherein each line is a program basic block, is employed to feed this voracious machine, and a multi-path prcfetch unit generates multiple cache accesses each cycle. Instructions are fully identified with Dynamic Instance Tags and move about the processor as independent entities. Kin supports multiexecution, where multiple paths, threads and processes are all executed simultaneously out of order. The processor has been designed using statecharts, and has been simulated running the SpecInt95 benchmark. We conclude that such complexity, which seems necessary for very high performance computing, is best achieved with an asynchronous architecture.

Multiple power saving methods were applied to a video processor for color digital video and still cameras. Architectural level methods failed to save power: asynchronous design, dynamic voltage scaling, bus switching minimization, pipeline stage merging, reduction of switching times and clock gating. However changing the algorithm to work on pixel differences yielded 3-15% power reduction in typical cases.

DLAP, an asynchronous pipeline with master-slave (dual) registers, offers improved performance. It is most suitable for converting synchronous circuits into asynchronous ones. DLAP is capable of truly decoupled operation: All pipeline stages can shift data simultaneously, and execution is faster than previous designs when variable delays are encountered. Implementations based on both edge triggered registers and transparent latches are shown. STG and verified controllers are presented and simulated.

The design of adaptive sensitivity CCD image sensor is described. The sensitivity of each pixel is individually controlled (by changing its exposure time) to assure that it is operating in the linear range of the CCD response, and not in the cut-off saturation regions. Thus, even though an individual CCD sensor is limited in its dynamic range, the whole CCD array has a much wider dynamic range. The idea is based on the biological retina principle of operation, enabling the imager to capture details in both the light and dark areas of high-contrast scenes, as in the human eye.

Traditional colour image enhancement techniques, have ignored the design of the human visual system and have treated colour images as three independent grayscale images. Contrary to this the authors first discuss an opponent colour model of the early visual system and demonstrate it's use in spatial enhancement of both image brightness and chroma. The opponent transform is calculated such that cone redundancies are reduced and information compressed, similar to the way it is performed in the visual system. This results in an achromatic and two opponent chromatic channels. Laplacian based edge enhancement is then performed independently on each channel. The spatial enhancement of chroma highlights small colour detail and enhances colour edges thus increasing image detail in areas where achromatic enhancement has no effect. Due to spatial limitations of the visual system, the best enhanced image is obtained when both achromatic and chromatic edge enhancement are used together.

Control Unit Synthesizer (CUS) is a language and a synthesizer for generating VLSI layouts of control units from a user's functional specification. CUS synthesizes multiple finite state machines (FSMs), which are organized hierarchically and interconnected by global variables and a FORK/JOIN protocol. High-level constructs like WHILE loops. FOR loops, registered and nonregistered variables, arbitrarily complex Boolean expressions, and nested statements allow the user to write descriptions of FSMs in a natural manner. The generated circuit is simulated at the logic-level using symbolic names. The resulting layout size is similar or better than manual layout.>

The authors propose a general synthesis method for efficiently implementing any family of Boolean functions over a set of variables, as a self-timed logic module. Interval temporal logic is used to express the constraints that are formulated for the self-timed logic module. A method is provided for proving the correct behavior of the designed circuit, by showing that it obeys all the functional constraints. The resulting circuit is compared with alternative proposed self-timed methodologies. This approach is shown to require less gates than other methods. The proposed method is appropriate for automatic synthesis of self-timed systems. A formal proof of correctness is provided.>

A self-timed finite state machine (FSM) is described. It is based on a formally proven, efficient implementation of self-timed combinational logic and a self-timed master-slave register. Temporal behavioral constraints are formalized, and the system is shown to abide by them. The synthesis method is algorithmic and serves as an automatic compiler of self-timed FSMs. The specification of the FSM is given by a state table, similar to that of synchronous machines. The circuit operates according to a sequence of events that replaces the role of the central clock in the synchronous FSM. The inputs and outputs of the circuit are double-rail (or ternary) and the circuit produces a completion signal. The method is compared with other approaches.>

Both biological and man-made (usually computer-based) vision systems have to acquire visual data and process it in real time at a formidable bit rate. To cope with this fundamental problem, biological systems of higher species employ mechanisms of data reduction already at the level of visual data acquisition.

A computer architecture for concurrent computing is proposed which has the shared memory aspect of tightly coupled multiprocessor systems and also the connection simplicity associated with message-connected, loosely-coupled multicomputer systems. A large address space is dynamically partitioned into contiguous segments that can be accessed by a single processor. The partitioning is accomplished by switching the system buses. The completion of a concurrent process is signaled by a processor's return to an idle state and the reattachment of its memory segment to the neighboring active processor. In effect, the assignment of an address sequence and the activation of a processor is a process-fork operation, and the processor deactivation and memory segment reattachment is a process-join. Following a description of the MP/C structure and operation, programming conventions are explained and demonstrated. Applications include tree-structured multiprocessing, recursive and nondeterministic procedures, very high precision numerical calculations, process-structured operating systems, and others. The linear MP/C structure is extensible to higher dimensions. A two-dimensional system is described and its application is discussed. Finally, performance issues are presented, and the MP/C architecture is compared with related designs.