This tutorial addresses the benefits one can take from deploying on-chip lifecycle management (OCLM) to design resilient Systems-in-Package (SiP). Such benefits are based on the massive deployment of on-chip cross-layer, collaborative sensors that are placed in strategic points of the chiplets and interposer, a data wrapper interface & management hub that is responsible to process and store the collected data from the sensors in a way to create an in-mission history of events, and on-chip analytics engine. The sensors can monitor from siliconlevel information (such as transistor aging, power-supply noise activity, electromigration, and transient faults in memory elements) up to system-level transactions in system bus, processor cores and memory IPs (e.g. task scheduling algorithm, and data and instructions fetched in memory). The sensors can be placed on dies on interposer. Furthermore, IEEE and IEC standards can be used to support data monitoring and collection processes. The analytics engine can be implemented based on simple/straightforward data structures such as Look-up Table (LUT) and Content-Addressable Memory (CAM), or be based on advanced Machine Learning/Artificial Intelligence (ML/AI) algorithms such as Dynamic Neural Network (DNN). The ultimate goal is to perform on-chip lifecycle management to trade, in-mission mode, power, performance, reliability and lifespan.

With the advancement of modern nanoscale technology nodes, Static Timing Analysis (STA) has become an indispensable technique for ensuring circuit reliability and performance across diverse process conditions. However, traditional STA methods scale poorly to the explosion of process corners in the nanoscale fabrication technology. Despite some seminal works in using AI to accelerate such processes, they either lack reliability or stability. To this end, we introduce ASAP, a novel approach addressing this challenge by combining both the latest deep learning methods and the classical Bayesian models to deliver scalable and accurate predictions with a self-calibration strategy to ensure reliability. Technically, the ASAP novelly integrates self-attention to help identify and prioritize crucial features under various input conditions and employs Neural Process to make confidence-based predictions for the final timing results. Furthermore, ASAP is equipped with Active Learning for self-refinement and self-correction. Experimental evaluations on benchmark circuits demonstrate that our method surpasses state-of-the-art work in STA accuracy by 18% in terms of prediction accuracy.

Reliable electronics plays a major role in shaping our daily lives, being a key enabler for critical applications, such as space missions, avionics, automotive, medicine, banking, automated industry, wireless communication networks, etc. However, design of highly reliable electronic systems remains a challenge with the advances in semiconductor technology and increase in integrated circuit (IC) complexity. In this work, we introduce the Horizon Europe Twinning project TWIN-RELECT, aimed at strengthening the scientific expertise in designing reliable integrated circuits. The paper presents the general project concept and objectives, and main directions of the joint research activities. The primary scientific goal is to contribute to the development of novel, more efficient, European Electronic Design Automation (EDA) tool-chain for design of reliable chips.

Process variation has proven to be one of the higher impacting factors in modern Application-Specific Integrated Circuit (ASIC) flows Quality of Results (QoR). On the one hand, the excessive MOSFET shrinking, in combination with the less potent metallization layers shrinking ability at cutting edge technology nodes, has rendered process variation effects more and more pronounced. On the other hand, the ever-increasing market competition between hi-tech semiconductor companies has promoted the adoption of immature, emerging technology nodes, which are not adequately calibrated for high yield in mass production. To cope with these issues, the industry has adopted a test-calibrate-produce strategy, meaning that design-specific golden silicon data are obtained by relatively inexpensive test chip fabrication runs and then are used to calibrate the ASIC flow for highest possible yield on expensive mass production, accordingly. These golden data are typically used at the ASIC flow Back-End, i. e. Place & Route, Clock Tree Synthesis, In-Place Optimization, Sign-Off. In this work, we present a deterministic and a Monte-Carlo based methodology, capable of providing an insight of inter-wafer and intra-die process variation impact, at the post-synthesis gate level, to provide a better initial solution to the ASIC Back-End. Both methodologies were tested using four open-source designs for 4 different technology libraries at 250, 130, 40, and 7 nm, and yield 9.74% improvement in total cell area and 22.14% improvement in leakage power, on average, over netlists synthesized at worst case, while meeting worst-case timing for all libraries. Also, our Monte-Carlo methodology provides a predictive view on the random variation impact on netlists synthesized at typical corner.

We demonstrate an iterative simulation-based maximum coverage detection and elimination analysis of logic-hazards for combinational logic loops. Although the focus is on asynchronous circuits with such feedbacks, it is apparent that the proposed approach can be practiced for every digital circuit with combinational loops. In regard to hazard detection, a simulation-based semi-modular analysis is presented, by extending the provided library technology behavioral Verilog files. For hazard elimination, only the standard cells within the paths causing a hazard have been included for analysis. The circuit becomes hazard-free by inserting buffers of the minimum required delay. We develop three path-based buffer insertion approaches; the more advanced ones model each logic gate and their relative timing constraints as a maximum set covering problem. The main characteristic of comparison is the count of inserted buffers and their total delay. The aforementioned hazard analysis is an iterative process, because the overall timing constraints of the circuit alter after each delay insertion. Experimental results indicate that the three hazard elimination approaches have various area penalties and their success rate ranges from 68.7% to 100%. Moreover, not all hazards can be resolved, mainly due to opposing constraints of sensitized hazard paths, and Boolean logic re-synthesis may be required.

In this article, unlike almost all state-of-the-art obfuscation solutions that focus on functional/logic obfuscation, we introduce a new paradigm, called data flow obfuscation, which exploits the essence of asynchronicity. In data flow obfuscation, by benefiting from the handshaking mechanism of asynchronous circuits, the system's FFs/latches will operate out of sync. Hence, the adversary has no sufficient knowledge to apply unrolling/BMC. Also, due to the inherited asynchronicity, the exact time of writing/capturing data into/from the scan chain becomes hidden. Hence, the SAT attack cannot be applied even while scan chain access is open. Moreover, our new proposed paradigm creates stateful/oscillating combinational cycles into the design which extensively boosts the difficulty of modeling this technique. We also demonstrate how data flow obfuscation could easily be integrated with any circuit at low overhead while there is no limitation such as compromising test flow.

As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models (CSMs) for accurate gate modeling. Industrial gate models, however, are precharacterized assuming capacitive loads, which poses significant challenges to the approximation of the highly resistive load interconnect with an effective capacitance ( Ceff). In fact, most related works are either computationally expensive or unable to approximate the output slew. Furthermore, they require additional precharacterization and ignore the Miller effect. In this article, we present an iterative methodology for fast and accurate gate delay estimation. The proposed approach accurately computes the driver output waveform, using closed-form formulas to calculate a Ceffper waveform segment, while accounting for their interdependence. Thus, it allows for variable analysis resolution exploiting an accuracy/runtime tradeoff. In contrast to prior works, our approach is compatible with conventional CSMs and considers the impact of Miller capacitance. We evaluate our method on representative driver-load test circuits consisting of interconnects with arbitrary RC characteristics and ASU ASAP 7-nm standard cells. The proposed method achieves 1.3% and 2.5% delay and slew root-mean-square percentage error (RMSPE) against SPICE, respectively. In addition, it provides high efficiency, as it converges in 2.3 iterations on average.

In this work, we compare alternative 3DIC partitioning methodologies, in terms of slack, number of inter-tier vias, Tier Area Ratio (TAR) and HPWL design parameters. The popular 3DIC postplacement, bin-based Fidducia-Mattheyses (FM) partitioning flow is used as a baseline for comparison. While the latter does produce a minimum number of inter-tier vias, for a specified FM area balance, their number cannot be directly constrained. This behavior motivated us to investigate a different 3DIC partitioning scheme, based on post-placement 3D legalisation, where the legaliser is capable of spreading cells across all available tiers for minimum displacement or HPWL. In contrast to bin-based FM, in 3D legalisation, the number of inter-tier vias can be directly constrained, albeit at the expense of TAR. The 3D legalisation partitioning scheme can expose a continuous trade off between the available number of intertier vias and design parameters. An unconstrained number of vias, which produce the best 3D gains in design parameters, while constraining the numbers of vias will trade them off with lower 3D gains. Results for three 3DIC partitioning flows are presented, on four OpenCores benchmarks, and the achieved trade offs between number of inter-tier vias and slack, TAR and HPWL parameters, per flow, are described.

Abax is a modern version of the classical Abacus, minimum displacement, greedy legaliser. Abax supports single-tier 2D or 3D legalisation for multiple, logic-on-logic 3D-IC tiers, efficient look-ahead legalisation of intermediate Global Placement (GP) iterations, Hard Macros, Blockages, row density constraints and multiple local cell displacement functions and cell orderings. For 3D-IC, Abax can produce multi-tier 3D-IC placements by performing Legalisation-based Partitioning. For efficient Look-ahead Legalisation, Abax supports two new local displacement cost functions, multi-cell mean and multi-cell total. We show that the classical single-cell displacement and multi-cell total can result in artifacts when legalising early intermediate GPs, and that multi-cell mean is the best candidate for Look-ahead Legalisation. Obstructions, i.e. Hard Macros and Blockages are handled by using two strategies. We present legalisation results for the ISPD2014 and ISPD2015 benchmarks, by using GP generated from Eh?Placer, and HPWL measurement by using RippleDP. For 3D, two-tier legalisation we illustrate a ~30% reduction in HPWL for a set of ISPD2014 benchmarks. For 2D legalisation on the ISPD2015 benchmarks, our average HPWL increase over GP is 3.03%, compared to 7.21% of the Eh?Placer legaliser, and 43.16% of the RippleDP legaliser.

FSM and PTnet control models are pertinent in both software and hardware applications as both specification and implementation models. The state-based, monolithic FSM model is directly implementable in software or hardware, but cannot model concurrency without state explosion. Interacting FSM models have so far lacked the formal rigor for expressing the synchronising interactions between different FSMs. The event-based, PTnet model is able to model both concurrency and choice within the same model, however lacks a polynomial time flow to implementation, as current methods of exposing the event state space require a potentially exponential number of states. In this work, we present a polynomial complexity flow for transforming a Free-Choice PTnet into a new formalism for Interacting FSMs, i.e Multiple, Synchronised FSMs (MSFSMs), a compact Interacting FSMs model, potentially implementable using any existing monolithic FSM implementation method. We believe that such a flow can in the long term bridge the event and state-based models. We present execution time and state space results of exercising our flow on 25 large PTnet specifications, describing asynchronous control circuits, and contrast our results to the popular Petrify tool for PTnet state space exploration and circuit implementation. Our results indicate a very significant reduction in both state space size and execution time.

BACKGROUND: Traditional strategies for selecting variables in high dimensional classification problems aim to find sets of maximally relevant variables able to explain the target variations. If these techniques may be effective in generalization accuracy they often do not reveal direct causes. The latter is essentially related to the fact that high correlation (or relevance) does not imply causation. In this study, we show how to efficiently incorporate causal information into gene selection by moving from a single-input single-output to a multiple-input multiple-output setting. RESULTS: We show in synthetic case study that a better prioritization of causal variables can be obtained by considering a relevance score which incorporates a causal term. In addition we show, in a meta-analysis study of six publicly available breast cancer microarray datasets, that the improvement occurs also in terms of accuracy. The biological interpretation of the results confirms the potential of a causal approach to gene selection. CONCLUSIONS: Integrating causal information into gene selection algorithms is effective both in terms of prediction accuracy and biological interpretation.

BACKGROUND: Genome scale expression profiling of human tumor samples is likely to yield improved cancer treatment decisions. However, identification of clinically predictive or prognostic classifiers can be challenging when a large number of genes are measured in a small number of tumors. RESULTS: We describe an unsupervised method to extract robust, consistent metagenes from multiple analogous data sets. We applied this method to expression profiles from five "double negative breast cancer" (DNBC) (not expressing ESR1 or HER2) cohorts and derived four metagenes. We assessed these metagenes in four similar but independent cohorts and found strong associations between three of the metagenes and agent-specific response to neoadjuvant therapy. Furthermore, we applied the method to ovarian and early stage lung cancer, two tumor types that lack reliable predictors of outcome, and found that the metagenes yield predictors of survival for both. CONCLUSIONS: These results suggest that the use of multiple data sets to derive potential biomarkers can filter out data set-specific noise and can increase the efficiency in identifying clinically accurate biomarkers.

MOTIVATION: Survival prediction of breast cancer (BC) patients independently of treatment, also known as prognostication, is a complex task since clinically similar breast tumors, in addition to be molecularly heterogeneous, may exhibit different clinical outcomes. In recent years, the analysis of gene expression profiles by means of sophisticated data mining tools emerged as a promising technology to bring additional insights into BC biology and to improve the quality of prognostication. The aim of this work is to assess quantitatively the accuracy of prediction obtained with state-of-the-art data analysis techniques for BC microarray data through an independent and thorough framework. RESULTS: Due to the large number of variables, the reduced amount of samples and the high degree of noise, complex prediction methods are highly exposed to performance degradation despite the use of cross-validation techniques. Our analysis shows that the most complex methods are not significantly better than the simplest one, a univariate model relying on a single proliferation gene. This result suggests that proliferation might be the most relevant biological process for BC prognostication and that the loss of interpretability deriving from the use of overcomplex methods may be not sufficiently counterbalanced by an improvement of the quality of prediction. AVAILABILITY: The comparison study is implemented in an R package called survcomp and is available from http://www.ulb.ac.be/di/map/bhaibeka/software/survcomp/.

Variability is one of the fundamental problems faced by nano-scale electronic circuits and is expected to become even worse as process technology scales. Desynchronization is a design methodology, which converts a synchronous gate-level circuit into a more robust asynchronous one. In this paper, we describe the first fully-automated desynchronization design flow, based only on contemporary synchronous EDA tools and a new point tool for performing the desynchronization transformation. The flow was used to implement, down to mask layout level, a simple pipelined processor in a 90nm industrial library. We show that the desynchronization methodology can be easily integrated into contemporary industrial EDA flows. Results, on the design implemented, indicate that desynchronized circuits exhibit increased variability tolerance and better average case performance, for a small area and power overhead.

FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. Actual-delay circuits operate according to the actual, physical device delays of the FPGA device components and not according to STA predictions, exhibit data-dependent delay,latency and output completion detection, and can thus detect when their outputs are ready to be latched. In this paper we demonstrate an FPGA flow, based around existing FPGA tools, capable of implementing actual-delay circuits, and through worst-case, upper-bound analysis show that such circuits exhibit reduced delay and higher performance than their conventional counterparts. The FPGA flow incorporates a logic synthesis transformation step for converting a conventional single-rail circuit to monotonic, dual-rail and a LUT mapper for mapping the latter to LUTs while preserving monotonicity. In addition, through our implementation of actual-delay circuits we are able to measure intra and inter-FPGA timing margins and we present results on the STA margin and timing deviation over four devices

Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock cycle accordingly. Desynchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus, permitting widespread adoption of asynchronicity without requiring special design skills or tools. In this paper, different protocols for desynchronization are first studied, and their correctness is formally proven using techniques originally developed for distributed deployment of synchronous language specifications. A taxonomy of existing protocols for asynchronous latch controllers, covering, in particular, the four-phase handshake protocols devised in the literature for micropipelines, is also provided. A new controller that exhibits provably maximal concurrency is then proposed, and the performance of desynchronized circuits is analyzed with respect to the original synchronous optimized implementation. Finally, this paper proves the feasibility and effectiveness of the proposed approach by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture

Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using a timed signal transition graph (STG) approach. In some cases, the problem can be solved by extracting all the delays and verifying whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Three different LDL ports are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner

This paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case study shows the applicability of the method and the potential benefits of de-synchronizing synchronous circuits.

This paper presents 3/spl Phi/LSSD, a novel, easily-automatable approach for scan insertion and ATPG of asynchronous circuits. 3/spl Phi/LSSD inserts scan latches only into global circuit feedback paths, leaving the local feedback paths of asynchronous state-storing gates intact. By employing a three-phase LSSD clocking scheme and complemented by a novel ATPG method, our approach achieves industrial quality testability with significantly less area overhead testing the same number of faults compared to full-scan LSSD. The effectiveness of our approach is demonstrated on an asynchronous SOC interconnection fabric, where our 3/spl Phi/LSSD ATPG tool achieved over 99% test coverage.

This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead and reasonable area and power overhead. We discuss various scenarios in which completion detection can be used to measure the delay of a synchronous circuit at fabrication time or at run time, and of an asynchronous circuit at run time. We conclude by showing, on a large set of benchmarks, the effectiveness of the proposed technique.

In this paper the automated design of an asynchronous DLX microprocessor is presented. The microprocessor has been designed beginning with a standard RTL-like Verilog specification and the Pipefitter design flow has been used to automatically generate both the specification for the direct implementation of the Control Unit and a synthesisable Verilog specification of the Data Path. The architecture of the DLX is locally synchronous and globally asynchronous and the delay elements for the generation of the local clock signal are automatically produced by Pipefitter as well.The following steps of the design flows (i.e., logic synthesis, technology mapping, placement and routing) have been completed using standard tools leading to the final layout of the circuit.The final microprocessor implements all the functionality of a standard DLX (with the exception of the floating point unit) and supports its whole set of instructions.Some considerations on the area occupation of the microcontroller will be presented in the last section of this paper.

This paper presents an approach by which asynchronous circuits can be realised with a conventional EDA tool flow and conventional standard cell libraries. Based on a gate-level asynchronous circuit implementation technique, direct-mapping, and by identifying the delay constraints and exploiting certain EDA tool features, this paper demonstrates that a conventional EDA tool flow can be used to describe, place, route and timing-verify asynchronous circuits.