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K. Skala

dblp:92/5187 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1986
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 81% Parallel and multicore computing · 19%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › bus-based interconnection
system bus		 0.011986
REYSM, A High Performance, Low Power Multi-Microprocessor Bus · ISCA 1986
Interconnection networks and networks-on-chip › arbitration
bus arbitration		 0.011986
REYSM, A High Performance, Low Power Multi-Microprocessor Bus · ISCA 1986
Parallel and multicore computing
multiprocessor system		 0.011986
REYSM, A High Performance, Low Power Multi-Microprocessor Bus · ISCA 1986
YearPublicationVenuePosition
1986 REYSM, A High Performance, Low Power Multi-Microprocessor Bus
abstract
In order to build lower cost multimicroprocessor systems, a narrow synchronous bus (15 active lines) is proposed. It multiplexes address and data on 8 bits, and arbitrates in two pipe-lined cycles on four lines. Due to the 20 to 40 MHz bus clock, and the pipelined control logic, the performances are equivalent to Multibus-2, IEEE-P896 and similar 32-bit buses. For the implementation, cards are disposed radially around a special connector. The very short connections allows for the usage of fast HC-MOS drivers with only a light adaptation.
Jean-Daniel Nicoud, K. Skala
 ISCA2