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James E. Bennett

dblp:92/564 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache design
0.011997
Prediction Caches for Superscalar Processors · MICRO 1997
Memory systems
cache miss prediction
0.011997
Prediction Caches for Superscalar Processors · MICRO 1997
Memory systems › cache
prefetching
0.011997
Prediction Caches for Superscalar Processors · MICRO 1997
YearPublicationVenuePosition
1997 Prediction Caches for Superscalar Processors
abstract
Processor cycle times are currently much faster than memory cycle times, and this gap continues to increase. Adding a high speed cache memory allows the processor to run at full speed as long as the data it needs is present in the cache. However, memory latency still affects performance in the case of a cache miss. Prediction caches use a history of recent cache misses to predict future misses and to reduce the overall cache miss rate. This paper describes several prediction caches, and introduces a new kind of prediction cache, which combines the features of prefetching and victim caching. This new cache is shown to be more effective at reducing miss rate and improving performance than existing prediction caches.
James E. Bennett, Michael J. Flynn
MICRO1