The rise of artificial intelligence (AI) in medical diagnostics has highlighted an essential need for transparent and interpretable systems, particularly in the field of mental health. The opaque decision-making in “black-box” AI models creates a challenge in clinical settings: they risk losing trust or causing uncritical reliance. This paradox jeopardizes mental healthcare, where skepticism or unwarranted confidence in AI can harm patient care. Effective explainability mechanisms are therefore essential not only to earn trust but to support responsible use by allowing clinicians to critically assess and verify AI-driven outputs. Thus, we propose a novel explainable AI (XAI) pipeline for automated depression diagnosis, designed to integrate both system-level and human-level interpretability. This dual approach is vital in clinical settings, as it combines rigorous statistical validation with clear, actionable insights that enhance practitioner confidence in AI-generated diagnoses. The pipeline leverages deep learning models for classification, augmented by traditional system-level XAI techniques and a Retrieval-Augmented Generation (RAG)-enhanced Large Language Model (LLM). With the integration of LLMs, the system translates abstract system-level explanations into understandable, natural language narratives. This provides a crucial cross-verification step that fosters calibrated trust: it mitigates the dual risks of under-trust, by providing a clear rationale, and over-trust, by flagging diagnostic inconsistencies within the AI models. This capability is critical for ensuring both user trust and satisfaction, as it empowers practitioners to critically assess and validate AI-driven insights. Through comprehensive human evaluations conducted by medical professionals, this approach demonstrates high alignment with clinical diagnostic indicators, underscoring the value of combining system-level and human-level explanations to make complex AI processes transparent and clinically meaningful. Validated across three diverse datasets-KangNing, EDAIC-WOZ, and CALLM-each presenting unique structural challenges from structured clinical inquiries to narrative-driven dialogues, our method bridges the gap between technical AI outputs and practitioner understanding, marking a significant advancement toward a trust-based, widely adoptable AI diagnostic tool in mental health care. By introducing a comprehensive framework for combining statistical rigor with narrative clarity, this work represents a critical step toward closing the gap between black-box AI systems and real-world clinical adoption. While our study is limited to depression diagnosis, the proposed framework illustrates a pathway toward explainable clinical AI systems. Future work may explore its adaptability to other medical contexts.

Guangya Wan, Yuqi Wu, Jie Chen, Sheng Li. Proceedings of the 2025 Conference of the Nations of the Americas Chapter of the Association for Computational Linguistics: Human Language Technologies (Volume 1: Long Papers). 2025.

The global prevalence of mental health disorders is increasing, leading to a significant economic burden estimated in trillions of dollars. In automated mental health diagnosis, the scarcity and imbalance of clinical data pose considerable challenges for researchers, limiting the effectiveness of machine learning algorithms. To cope with this issue, this paper aims to introduce a novel clinical transcript data augmentation framework by leveraging large language models (CALLM). The framework follows a "patient-doctor role-playing" intuition to generate realistic synthetic data. In addition, our study introduces a unique "Textbook-Assignment-Application" (T-A-A) partitioning approach to offer a systematic means of crafting synthetic clinical interview datasets. Concurrently, we have also developed a "Response-Reason" prompt engineering paradigm to generate highly authentic and diagnostically valuable transcripts. By leveraging a fine-tuned DistilBERT model on the E-DAIC PTSD dataset, we achieved a balanced accuracy of 0.77, an F1-score of 0.70, and an AUC of 0.78 during test set evaluations, which showcase robust adaptability in both Zero-Shot Learning (ZSL) and Few-Shot Learning (FSL) scenarios. We further compare the CALLM framework with other data augmentation methods and PTSD diagnostic works and demonstrates consistent improvements. Compared to conventional data collection methods, our synthetic dataset not only demonstrates superior performance but also incurs less than 1% of the associated costs.

Depression is increasingly impacting individuals both physically and psychologically worldwide. It has become a global major public health problem and attracts attention from various research fields. Traditionally, the diagnosis of depression is formulated through semi-structured interviews and supplementary questionnaires, which makes the diagnosis heavily relying on physicians’ experience and is subject to bias. However, since the pathogenic mechanism of depression is still under investigation, it is difficult for physicians to diagnose and treat, especially in the early clinical stage. As smart devices and artificial intelligence advance rapidly, understanding how depression associates with daily behaviors can be beneficial for the early stage depression diagnosis, which reduces labor costs and the likelihood of clinical mistakes as well as physicians bias. Furthermore, mental health monitoring and cloud-based remote diagnosis can be implemented through an automated depression diagnosis system. In this article, we propose an attention-based multimodality speech and text representation for depression prediction. Our model is trained to estimate the depression severity of participants using the Distress Analysis Interview Corpus-Wizard of Oz (DAIC-WOZ) dataset. For the audio modality, we use the collaborative voice analysis repository (COVAREP) features provided by the dataset and employ a Bidirectional Long Short-Term Memory Network (Bi-LSTM) followed by a Time-distributed Convolutional Neural Network (T-CNN). For the text modality, we use global vectors for word representation (GloVe) to perform word embeddings and the embeddings are fed into the Bi-LSTM network. Results show that both audio and text models perform well on the depression severity estimation task, with best sequence level$F_{1}$score of 0.9870 and patient-level$F_{1}$score of 0.9074 for the audio model over five classes (healthy, mild, moderate, moderately severe, and severe), as well as sequence level$F_{1}$score of 0.9709 and patient-level$F_{1}$score of 0.9245 for the text model over five classes. Results are similar for the multimodality fused model, with the highest$F_{1}$score of 0.9580 on the patient-level depression detection task over five classes. Experiments show statistically significant improvements over previous works.

This paper presents a portable biosensing system consisting of a bioimpedance measurement circuit and an IDE chip. This system can be modified to detect various biomolecules, including DNA, antigen/antibody, proteins, metabolites, etc. The bioimpedance measurement circuit has a fast measurement speed (obtaining single frequency impedance result within 1.1 miliseconds), and its error levels are within 0.5% and 0.1% in terms of accuracy and precision, respectively. The proposed system can function similarly to the commercialized electrochemical workstation (Biologic SP-200). Meanwhile, the proposed system is 36 times faster in terms of measurement from 10 Hz to 1 MHz (72 seconds vs 3 seconds). Furthermore, the system has the potential to be a point-of-care diagnostic tool because of its low-cost and portability.

Discrete Cosine Transform (DCT) is a commonly used building block for image and video compression. In this article, we present a Markov Random Field (MRF)-based design for DCT implementation because MRF logic gates outperform standard non-MRF units by achieving high noise immunity for applications to logic-based computing systems in deep sub-micron condition. Furthermore, it is found that stochastic logic, a low-cost form of number representation, can also efficiently simplify computations. By combining these two techniques, we present an improved DCT hardware circuit. The example eight-point one-dimensional DCT (1D DCT) system is simulated using 65 nm CMOS technology. Simulation results show that the proposed MRF design can achieve 13% higher noise immunity and 47% area saving, compared with the typical stochastic 1D DCT using classical Master-and-Slave architecture. While achieving the same error rate of 0.21, power consumption is reduced by 52%.

Markov Random Field (MRF) has been adopted to achieve high noise immunity for computing systems in deep sub-micron condition. However, complete MRF designs consume large area overhead, limiting its direct hardware implementation for one-dimensional discrete cosine transform. As a low-cost number representation, stochastic logic can efficiently simplify computing circuits. By combining the two techniques, we present an MRF-based gate group design in order to achieve area and power saving with high noise immunity for stochastic adders used in discrete cosine transform. To validate the performance of our design, we implement an 8-point one-dimensional discrete cosine transform (1D-DCT) system applied the proposed design in 65 nm CMOS technology. Simulation results show that the proposed design can achieve 7% higher noise-immunity with 31% area-saving for stochastic adders and 52% power-saving, compared with the area-saving Master-and-slave stochastic 1D-DCT. The proposed design benefits outdoor sensors and biological portable devices dealing with image compression.

A charge pump with enhanced output voltage pumping gain and efficiency for low-voltage applications is proposed in this paper. Except for threshold voltage drop and body effect, another factor that limits voltage pumping efficiency is undesired charge transfer. The proposed charge pump circuit utilizes charge transfer switches to eliminate the effects of threshold voltage drop and body effect. Moreover, a complementary branch scheme is applied to reduce undesired charge transfer in order to further improve the pumping efficiency. Simulation results demonstrate better pumping performance of the proposed charge pump circuit compared with other circuits.

Parallelizing the memory accesses in a nested loop is a critical challenge to facilitate loop pipelining. An effective approach for high-level synthesis on field-programmable gate array is to map these accesses to multiple on-chip memory banks using a memory partitioning technique. In this paper, we propose an efficient memory partitioning algorithm with low overhead and low time complexity for parallel data access via data reuse. We find that for most applications in image and video processing, a large amount of data can be reused among different iterations of a loop nest. Motivated by this observation, we propose to cache reusable data using on-chip registers, organized as register chains. The nonreusable data are then separated into several memory banks by a memory partitioning algorithm. We revise the existing padding method to cover cases occurring frequently in our method wherein certain components of partition vector are zeros. Experimental results have demonstrated that compared with the state-of-the-art algorithms, the proposed method is efficient in terms of execution time, resource overhead, and power consumption across a wide range of access patterns extracted from applications in image and video processing. As for the testing patterns, the execution time is typically less than one millisecond. And the number of required memory banks is reduced by 59.7% on average, which leads to an average reduction of 78.2% in look-up tables, 65.5% in flip-flops, 37.1% in DSP48Es, and therefore 74.8% reduction in dynamic power consumption. Moreover, the storage overhead incurred by the proposed method is zero for most widely used access patterns in image filtering.

This paper provides a new scheme for the VLSI implementation of a parallel Discrete Cosine Transform (DCT) using stochastic logic. Stochastic computation is a number representation, which can carry out complex computations with very low hardware cost. However, the delay of data output is proportional to the length of serial sequence. We provide a new area-saving parallel DCT design to improve the system throughput by using our proposed stochastic OR-adder and OR-AND-adder. Results show the proposed parallel stochastic DCT can meet the requirement of image processing while maintaining a ± 5% performance difference compared to the traditional DCT implementation. Our synthesized chip design using the TSMC CMOS 130nm technology also shows that the proposed parallel stochastic DCT is at least 10 times more efficient in area and delay than that of the traditional DCT and the serial stochastic DCT.

As the size of CMOS devices continues to scale down, the reliability of circuits becomes one of main challenges in low supply voltage designs. Markov Random Field (MRF) circuits, a probabilistic-based approach, can achieve higher noise immunity compared to traditional designs under conditions of ultra-low supply voltage and low threshold voltage. However, the basic MRF elements have complex structures and become a stringent factor that limits MRF-based VLSI design. In this paper, we provide a partial-clique-energy MRF (PMRF) design method, trading off the noise immunity for area efficiency. We then propose an Enhanced PMRF (EPMRF)-pair for multi-level and multi-function joint PMRF designs. The main idea is to use the joint clique energy of two complementary partial clique energies to make up performance losses. The measurement results show that, the proposed EPMRF pair can operate at 0.25 V with 10-4 dB output noise power with 5.6 dB input signal-noise ratio (SNR). With the 130 nm CMOS technology, the chip of our EPMRF based carry-look-ahead adder achieves 29% area-saving and 55% energy-saving compared to existing ultra-low supply voltage fault tolerant designs.

As the world's population ages, healthcare costs become heavy burdens worldwide. Portable point-of-care diagnostic devices, such as glucose meters, can significantly reduce the costs associated with patient care. There are many of small biological molecules present in biological samples which are of interest in healthcare applications. In this paper, a simple low-cost impedance detection circuit has been designed to detect different biomolecules such as DNA, proteins and other metabolites. In particular, the impedance across an electrode will change due to the binding of target biomolecules and gold nanoparticles. Experimental results show that the device can measure impedance changes with accuracy in the range of ±3%.

This article provides a brief overview and background on current biosensor designs for applications in genomics, proteomics and metabolomics. As research continues in many different aspects of biosensor design, new and better ways to recognize and detect low concentrations of a wide variety of different biomolecules are being developed for various applications. Biosensors can offer a simpler, faster and cheaper alternative to the testing that is often required to collect the large amounts of data for genomic, proteomic and metabolomic sensing. Recognition elements such as DNA aptamers make detecting very different types of biomolecules in the same system possible, while the use of signal-enhancing nanoparticle probes and microfabricated sensor arrays make it possible to test for a large number of different target biomolecules quickly and effectively.

This paper describes the design, characterization, and testing of a close-proximity, real-time thermoacoustic sensor for ultrasound intensity measurements. Plexiglass sensors, 20 mm diameter and 3.3 mm length, absorbed ultrasound with a frequency of 1.5 MHz, a 20% duty cycle, and a 1 kHz pulse repetition frequency, at intensities between 30 and 100 mW/cm2. An embedded system design fit thermistor temperature data to a curve relating the temperature rise averaged across the backside of the sensor to the applied ultrasound intensity, and calculated the corresponding ultrasound intensity. Good linearity was demonstrated between the ultrasound intensity measured using a radiation force balance, and intensity measured using the thermoacoustic sensor when placed in contact with the acoustic transducer: accuracy within 5% of the target value and standard deviation of 4.55% or less. The sensor has an operational temperature range of 22°C to 26°C. This design makes for a quick and convenient method of checking ultrasound intensity, and also presents the possibility of integrated sensor and ultrasound generator systems using feedback loops to achieve auto-calibration.

Sonodyanmic Therapy (SDT) is a new type of cancer therapy and has attracted lots of research attention recently. In this article, we present how nano-formulation helped SL052 to form a water soluble sono/photo-sensitize nanoparticle (SL052-NPs) for cancer treatment. The nanostructure formation encapsulates SL052 and greatly improves the SL052 physicochemical properties without modifying its chemical structure. Nano-formulation also helps SL052 to achieve deep-site cancer delivery, image function for diagnosis, and ultrasound or photo controlled localized cancer therapy.

This paper presents the design and implementation of a Low-Intensity Pulsed Ultrasound (LIPUS) generator for dental tissue regeneration. It consists of a power supply subsystem, an ultrasonic transducer, an impedance-matching circuit and an integrated circuit consisting of digital controller circuitry and driver circuit. The integrated circuit was designed and fabricated using 0.8µm High-Voltage Technology from Dalsa Semiconductor Inc. The power supply sub-system and impedance matching network are implemented using discrete components. Upon construction, the LIPUS generator was verified to function correctly and is capable of producing LIPUS power upwards of 100mW in the vicinity of the transducer';s resonance frequency. Power efficiency of the circuitry, excluding the power supply sub-system, is estimated at 70%.

The continued miniaturization of silicon-based electronic circuits is fast approaching its physical limitations. It is unlikely that advances in miniaturization, following the so-called Moore's Law, can continue in the foreseeable future. Nanoelectronics has to go beyond silicon technology. New device paradigms based on nanoscale materials, such as molecular electronic devices, spin devices and carbon-based devices, will emerge. In this article, we introduce a nanodevice paradigm: graphene nanoelectronics. Due to its unique quantum effects and electronic properties, researchers predict that graphene-based devices may replace carbon nanotube devices and become major building blocks for future nanoscale computing. To manifest its unique electronic properties, we present some of our recent designs, namely a graphene-based switch, a negative differential resistance (NDR) device and a random access memory array (RAM). Since these basic devices are the building blocks for large-scale circuits, our findings can help researchers construct useful computing systems and study graphene-based circuit performance in the future.

Conventional ultrasound designs are used for medical therapeutics including different tissue healing and medical imaging. Recently, we discovered that the low intensity pulsed ultrasound (LIPUS) can help stimulate dental and bone tissue growth. However, the size of available ultrasound devices is too large to fit inside the mouth.,. In this paper, we present the design of a system-on-chip ultrasonic device for dental tissue formation and stem cell growth differentiation. The device helps tissue healing by stimulating formation of new blood vessels and different tissue matrix formation, like bone, dentin and cementum. Testing results show that our prototype device can stimulate stem cells to grow and differentiate into bone forming cells.

As silicon circuits quickly approach their physical limitations, researchers are actively looking for novel building blocks to develop nanocircuits. However, future nanoelectronic circuits are more error-prone than conventional CMOS designs because of their self-assembly design. To help design fault-tolerant nanoscale circuits, new circuit design and testing tools are needed. In this paper, an efficient methodology to evaluate nanoscale circuit fault tolerance based on belief propagation (BP) algorithm is proposed. Compared with existing approaches, the BP algorithm is more efficient in terms of memory requirements and CPU times. The proposed methodology can be easily run on multiple CPUs to achieve parallel processing and thus further reduces simulation time.

We demonstrated that an electronic field-effect transistor (FET) can be made from patterned monolayer or bilayer graphene nanoribbons. The FET performance can be achieved regardless of structural defects (either edge defects or topological defects). The I-V characteristics of resulting FETs are similar to those made from single-walled carbon nanotubes. This one-dimensional functional device is very useful for future nanoscale electronics.

As people live longer in the new millennium, it becomes a necessity to develop affordable technologies to improve the quality of life. This paper provides an overview of such techniques in drug delivery and clinical care, namely: (i) health care from organ functions to the cell behaviors; (ii) the development of implantable biosensors and instrumentation; (iii) the process and visualization systems; and (iv) nanotechnology for drug delivery. The goal is to stimulate cross-disciplinary research in the circuits and systems society aimed towards optimal clinical care and personalized therapeutic intervention.

Two probabilistic-based models, namely the ensemble-dependent matrix model (Chen and Li, 2006), (Patel et al., 2003) and the Markov random field model (Chen et al., 2003), have been proposed to deal with faults in nanoscale system. The MRF design can provide excellent noise tolerance in nanoscale circuit design. However, it is complicated to be applied to model circuit behavior at system level. Ensemble dependent matrix methodology is more effective and suitable for CAD tools development and to optimize nanoscale circuit and system design. In this paper, we show that the ensemble-dependent matrices describe the actual circuit performances when signal errors are present. We then propose a new criterion to compare circuit error-tolerance capability. We also prove that the matrix model and the Markov model converge when signals are digital

Breast cancer is the most common form of cancer in women worldwide. The major impediment to finding cures for malignant breast cancers is the development of resistances to therapeutic treatments by tumors. The development of nanoparticles may provide an important opportunity for improvement in breast cancer treatments. Nanoparticles coupled with the specific targeting agents have the ability to track and eliminate breast cancer cells. In this paper, we present gold-based nanoparticles for breast cancer diagnosis and treatment. The proposed design can become a new method for the treatment of breast cancer tumors. Our design can eventually lead to clinical trials which will benefit breast cancer patients worldwide.

In this paper, we propose to use ensemble dependent matrices for describing combinatorial nanoscale circuits. We then apply various signal-processing techniques, including eigen analysis, and the use of mutual information, for hardware-efficient fault-tolerant nanoscale design at the system level. We find that the condition of an ensemble matrix product determines the circuit's fault-tolerant capability. If the product matrix is ill-conditioned, the combinatorial circuit is more error-prone. The knowledge gained from this project can be used eventually to develop computer-aided design tools for optimal nanoscale circuit and system design

Adopting ultra-short impulses in ultra-wide bandwidth (UWB) transmission make systems vulnerable to timing-jitter. To overcome this challenge, we propose a timing-hopping high-order waveform modulation scheme in this letter. Central to our design is the adaptation of a high-order monocycle (HOM) that can provide timing-jitter robust UWB communications.

An important aspect of wireless networks is dynamic behavior. In this paper, we propose a joint cross-layer design for QoS (quality of service) content delivery. Central to our proposed cross-layer design is the concept of adaptation. We propose QoS-awareness scheduler and power adaptation scheme at both uplink and downlink medium access control (MAC) layer to coordinate the behavior of the lower layers for resource efficiency. The test results show that our cross-layer design provides a good scheme for wireless QoS content delivery.

An approach of joint blind estimation of the symbol timing offset and carrier frequency offset using multiple orthogonal frequency-division multiplexing (OFDM) symbols is proposed for OFDM systems in frequency selective fading environments. The proposed approach greatly improves the estimation accuracy of the synchronization parameters, more than the ML estimation of N. Lashkarian and S. Kiaei (see IEEE Trans. Commun., vol.48, p.2139-49, 2000). This conclusion is derived from analyzing their performances. Meanwhile, simulation shows that estimation of symbol timing is completely correct for signal-to-noise ratio (SNR) as low as 0 dB, and the variance of the frequency offset estimator is nearly close to its Cramer-Rao bound (CRB) with varying SNR.

In this paper, we propose "cross layer" design, such as swift-OFDM, low-latency packet-awareness coder and adaptive noise filtering design for wireless multimedia delivery. Unlike the conventional error correction code, we take the bursty nature of wireless Internet into our coder design consideration. Furthermore, we adoptively filter out noise based on image content so that we can reduce noise for least visual distortion. The experiment results show that the proposed design results in better video quality.

In this paper, the FH-OFDM (fast hopping OFDM) design and its associated packet-awareness channel coder are presented for wireless multimedia. In addition, the effectiveness of the coder over Markov channel model is studied. The simulations show that these proposed techniques can achieve significant performance gains.

We present a panorama picture on how to achieve end-to-end video over IP service under the communication environments, consisting of backbone networks, hybrid access networks, and the end users. The paper consists of three equally weighted subtopics which cover some novel thoughts in designing and implementing the video over IP system in the different areas, namely, a Synchronous Optical NETwork (SONET) network adapter for backbone connections, the joint source-channel multistream coding in hybrid access networks, and the content-based source coding in the transform domain. We propose to link the three different problems associated with the hybrid networks, which have different characteristics and design requirements, to improve the critical performances in various areas of video over IP systems. The goal is to deliver video over IP networks in more cost-effective and reliable manner. IP/ATM over SONET is currently a commonly used backbone technique. In the first part of this paper, we present a flexible design and implementation of a SONET network adapter to carry IP traffic via optical fiber. Unlike many conventional designs, our single-chip implementation supports different data rates (OC-3, OC-12, and OC-48), carries IP traffic directly over fiber, achieves more flexible for multivendor interoperability, and provides bandwidth efficient designs at the lower system latency. Hybrid access-networks via wireline or wireless connections are most likely needed for last-mile services. In the second part of this paper, we propose a joint source-channel multistream video coding scheme to combat the transmission errors under the harsh network conditions. On top of traditional error control techniques, the simulation results demonstrate that our multistream design outperform the conventional approaches by up to 5-7 dB under the harsh network conditions. To support our multistream video coding scheme, we need to access and manipulate video objects rather than the frame of pixels. In the third part of this paper, we focus on the coding of arbitrary shape video fully in the transform domain.

By doubling the accuracy of motion compensation from integer-pel to half-pel, we can significantly improve the coding gain. Therefore, in this paper, we propose a novel COordinate Rotation Digital Computer (CORDIC) architecture for combined design of discrete cosine transform (DCT) and half-pel motion estimation. Unlike the conventional block matching approaches based on interpolated images, our CORDIC design can directly extract motion vectors at half-pel accuracy in the transform domain without interpolation. Compared to the conventional block matching methods with interpolation, our multiplier-free design achieves significant hardware saving and far less data flow. Our emphasis in this paper is on achieving efficient design of video coding engine by minimizing computational units along the data path. Furthermore, we implement the embedded design on a dedicated single chip to demonstrate its performance. The DCT-based nature of our design enables us to efficiently combine both DCT and motion estimation units, which are the two most important components of many multimedia standards consuming more than 80% of computing power for a video coder, into one single component. As a result, we can provide a single chip solution for video coding engine while many conventional designs may require multiple chips. In addition, all multiply-and-add (MAC) operations in plane rotations are replaced by CORDIC processors with simple shift-and-add, which is quite simple and compact to realize while being no slower than the bit serial multipliers widely proposed for VLSI array structures. Based on the test result, our chip can operate at 20 MHz with 0.8-/spl mu/m CMOS technology. Overall, we provide a low-complexity, high throughput solution in this paper for MPEG-1, MPEG-2, and H.263 compatible video codec design.

The explosive growth in Internet traffic has created the need to transport packets such as IP paradigm over high-speed links. Packets over SONET or directly over optical fiber technology is, therefore, being deployed today in backbone networks to provide efficient, cost-effective, high-speed transport between fast routers. In this paper, a flexible design and implementation of this technology has been proposed. Our design can support up to OC-48 (2.4 Gb/s) data rate with negligible system latency, which is very suitable for real-time multimedia applications.

Low power as a de facto is one of the most important criteria for many signal-processing system designs, particularly in multimedia cellular applications and multimedia system on chip design. There have been many approaches to achieve this design goal at many different implementation levels ranging from very-large-scale-integration fabrication technology to system design. In this paper, the multirate low-power design technique will be used along with other methods such as look-ahead, pipelining in designing cost-effective low-power architectures of compressed domain video coding co-processor. Our emphasis is on optimizing power consumption by minimizing computational units along the data path. We demonstrate both low-power and high-speed can be accomplished at algorithm/architecture level. Based on the calculation and simulation results, the design can achieve significant power savings in the range of 60%-80% or speedup factor of two at the needs of users.

Low power and high performance are the two most important criteria for many signal-processing system designs, particularly in real-time multimedia applications. There have been many approaches to achieve these two design goals at many different implementation levels ranging from very-large-scale-integration fabrication technology to system design. We review the works that have been done at various levels and focus on the algorithm-based approaches for low-power and high-performance design of signal processing systems. We present the concept of multirate computing that originates from filterbank design, then show how to employ it along with the other algorithmic methods to develop low-power and high-performance signal processing systems. The proposed multirate design methodology is systematic and applicable to many problems. We demonstrate that multirate computing is a powerful tool at the algorithmic level that enables designers to achieve either significant power reduction or high throughput depending on their choice. Design examples on basic multimedia processing blocks such as filtering, source coding, and channel coding are given. A digital signal-processing engine that is an adaptive reconfigurable architecture is also derived from the common features of our approach. Such an architecture forms a new generation of high-performance embedded signal processor based on the adaptive computing model. The goal of this paper is to demonstrate the flexibility and effectiveness of algorithm-based approaches and to show that the multirate approach is an effective and systematic design methodology to achieve low-power and high throughput signal processing at the algorithmic and architectural level.

Based on the concept of pseudo-phase and the sinusoidal orthogonal principles, we design a novel low-complexity and high throughput CORDIC (COordinate Rotation Digital Computer) architecture for half-pel motion estimation. The proposed multiplier-free and fully-pipelined parallel architecture works solely at DCT domain without interpolation of input images to meet the needs of high-quality high-bit rate video communications. In addition, the DCT-based nature enables us to efficiently combine the DCT and motion estimator into one single component of relatively low complexity. Its regular and modular structure along with only local interconnection provides a low-complexity solution for MPEG-2 and H.263 compatible video codec design on a dedicated single chip.