Small-signal models of pulse-width modulation (PWM) converters are widely used for analyzing stability and play an important role in converter design and control. However, existing small-signal models either are based on averaged DC behaviors, and hence are unable to capture frequency responses that are faster than the switching frequency, or greatly approximate these high-frequency responses. We address the severe limitations of the existing models by proposing a multiharmonic model that provides a complete small-signal characterization of both DC averages and high-order harmonic responses. The proposed model captures important high-frequency overshoots and undershoots of the converter response, which are otherwise unaccounted for by the existing techniques. In two converter examples, the proposed model corrects the misleading results of the existing models by providing truthful characterization of the overall converter AC response and offers important guidance for converter design and closed-loop control.

The emergence of multicore and many-core processors has introduced new opportunities and challenges to electronic design automation research and development. While the availability of increasing parallel computing power holds new promise to address many challenges in computer-aided design (CAD), the leverage of hardware parallelism can only be possible with a new generation of parallel CAD applications. In this paper, we propose a novel hierarchical multialgorithm (MA) parallel circuit simulation approach and its multicore implementation to expedite one of the most fundamental CAD applications: transistor-level transient circuit simulation. In our parallel circuit simulation approach, we create two levels of parallelism. At the higher level of parallelism, we start multiple simulation algorithms in parallel for a given simulation task. Interalgorithm communication is established to enable simulation algorithms to exchange useful information so that they could advance faster than without doing so. At the lower level of parallelism, each algorithm within the MA framework utilizes fine-grained parallel techniques such as parallel device evaluation and parallel matrix solve to fully harness the available hardware resources. By combining the two levels of parallelism, the computing power of the multicore or many-core processor platforms can be fully utilized to achieve superlinear speedup in circuit simulation.

In this article, a parallel transient circuit simulation approach based on an adaptively-controlled time-stepping scheme is proposed. Different from the widely-used implicit numerical integration techniques in most transient simulators, this work exploits the recently-developed explicit telescopic projective numerical integration method for efficient parallel circuit simulation. Because telescopic projective integration addresses the well-known stability issue of explicit numerical integrations by adopting combinations of inner integrators and outer integrators in a multilevel fashion, the simulation time-step is no longer limited by the smallest time constant in the circuit. With dynamic control of telescopic projective integration, the proposed projective integration framework not only leads to noticeable efficiency improvement in circuit simulation, it also lends itself to straightforward parallelization due to its explicit nature. The latter has led to encouraging runtime efficiencies, observed on shared-memory parallel platforms. In addition to solving standard initial-value problems (IVPs) of differential equations, the same telescopic integration framework is adopted for solving final-value problems (FVPs), where the system is integrated backwards in time. Through a new elegant formulation, we show how an IVP and FVP can be simultaneously solved to allow for a coarse-grained bidirectional parallel circuit simulation scheme. Such a bidirectional approach is demonstrated in the context of parallel shooting-Newton-based steady-state circuit analysis. The proposed bidirectional approach has unique and favorable properties: the solutions of the two ODE problems are completely data-independent with built-in automatic load balancing.

This work exploits the recently developed telescopic projective numerical integration method for efficient parallel circuit simulation. Stable explicit numerical integration is achieved by adopting an explicit inner integrator (e.g. forward Euler) in a multi-level telescopic projective framework, thereby addressing the well-known stability limitation of many explicit numerical integration methods. In the presented approach, the effective time step of the entire multilevel integration is no longer limited by the smallest time constant of the circuit so as to safeguard stability. Rather, it is controlled solely by the accuracy requirement. This makes it possible to explore the natural parallelizability of such explicit integration method for parallel circuit simulation. We demonstrate the potential of the presented approach and its parallel implementation on multi-core machines with encouraging initial results.

While solving initial-value ODEs is the de facto approach to time-domain circuit simulation, the opposite act, solving final-value ODEs, has been neglected for a long time. Stable numerical integration of initial-value ODEs involves significant complications; the application of standard integration methods simply leads to instability. We show that not only practically meaningful applications of final-value ODE problems exist, but also the inherent stability challenges may be addressed by recently proposed numerical methods. Furthermore, we demonstrate an elegant bi-directional parallel circuit simulation scheme, where one time-domain simulation task is sped up by simultaneously solving initial and final-value ODEs, one from each end of the time axis. The proposed approach has unique and favorable properties: the solutions of the two ODE problems are completely data independent with built-in automatic load balancing. As a specific application study, we demonstrate the proposed technique under the contexts of parallel digital timing simulation and the shooting-Newton based steady-state analysis.

In this paper, we present a parallel harmonic-balance approach, applicable to the steady-state and envelope-following analyses of both driven and autonomous circuits. Our approach is centered on a naturally parallelizable preconditioning technique that speeds up the core computation in harmonic-balance-based analysis. As a coarse-grained parallel approach by algorithm construction, the proposed method facilitates parallel computing via the use of domain knowledge and simplifies parallel programming compared with fine-grained strategies. The proposed parallel preconditioning technique can be combined with more conventional parallel approaches such as parallel device model evaluation, parallel fast Fourier transform operation, and parallel matrix-vector product to further improve runtime efficiency. In our message-passing-interface-based implementation over a cluster of workstations and multithreading-based implementation on a shared-memory machine, favorable runtime speedups with respect to the conventional serial approaches and the serial implementations of the same parallel algorithms are achieved.

While the emergence of multi-core shared-memory machines offers a promising computing solution to ever complex chip design problems, new parallel CAD methodologies must be developed to gain the full benefit of these increasingly parallel computing systems. We present a parallel transient simulation methodology and its multi-threaded implementation for general analog and digital ICs. Our new approach, Waveform Pipelining (abbreviated as WavePipe), exploits coarsegrained application-level parallelism by simultaneously computing circuit solutions at multiple adjacent time points in a way resembling hardware pipelining. There are two embodiments in WavePipe: backward and forward pipelining schemes. While the former creates independent computing tasks that contribute to a larger future time step by moving backwards in time, the latter performs predictive computing along the forward direction of the time axis. Unlike existing relaxation methods, WavePipe facilitates parallel circuit simulation without jeopardying convergence and accuracy. As a coarse-grained parallel approach, WavePipe not only requires low parallel programming effort, more importantly, it creates new avenues to fully utilize increasingly parallel hardware by going beyond conventional finer grained parallel device model evaluation and matrix solutions.

Technology scaling in sub-100 nm regime has significantly shrunk the SRAM stability margins in data retention, read and write operations. Conventional static noise margins (SNMs) are unable to capture nonlinear cell dynamics and become inappropriate for state-of-the-art SRAMs with shrinking access time and/or advanced dynamic read-write-assist circuits. Using the insights gained from rigorous nonlinear system theory, we define the much needed SRAM dynamic noise margins (DNMs). The newly defined DNMs not only capture key SRAM nonlinear dynamical characteristics but also provide valuable design insights. Furthermore, we show how system theory can be exploited to develop CAD algorithms that can analyze SRAM dynamic stability characteristics three orders of magnitude faster than a brute-force approach while maintaining SPICE-level accuracy. We also demonstrate a parametric dynamic stability analysis approach suitable for low-probability cell failures, leading to three orders of magnitude runtime speedup for yield analysis under high-sigma parameter variations.

The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing parallel computing power holds new promise to address many computing challenges in CAD, the leverage of hardware parallelism can only be possible with a new generation of parallel CAD applications. In this paper, we propose a novel multi-algorithm parallel circuit simulation approach (MAPS) and its multi-core implementation to expedite one of the most fundamental CAD applications: transistor-level transient circuit simulation. MAPS starts multiple simulation algorithms in parallel for a given simulation task. By properly synchronizing these algorithms on-the-fly, we exploit the diversity in simulation algorithms to achieve possibly superlinear overall speedup in transient simulation. In addition, our unique multi-algorithm framework allows unique safe exploration of simulation methods that are conventionally discarded due to convergence concerns. As a coarse grained parallel simulation approach, the implementation of MAPS demands a minimum of parallel programming effort and allows for reuse of existing serial simulation codes.

Increasing variability in modern manufacturing processes makes it important to predict the yields of chip designs at early design stage. In recent years, a number of statistical static timing analysis (SSTA) and statistical circuit optimization techniques have emerged to quickly estimate the design yield and perform robust optimization. These statistical methods often rely on the availability of statistical process variation models whose accuracy, however, is severely hampered by the limitations in test structure design, test time, and various sources of inaccuracy inevitably incurred in process characterization. To consider model characterization inaccuracy, we present an efficient importance sampling based optimization framework that can translate the uncertainty in process models to the uncertainty in circuit performance, thus offering the desired statistical best/worst case circuit analysis capability accounting for the unavoidable complexity in process characterization. Furthermore, our new technique provides valuable guidance to process characterization. Examples are included to demonstrate the application of our general analysis framework under the context of SSTA.

An efficient parallelizable hierarchical preconditioning framework is proposed to accelerate the simulation of analog and RF circuits using Harmonic Balance (HB). We show that the proposed hierarchical preconditioning scheme not only brings significant runtime speedup over the conventional block diagonal (BD) preconditioner for driven circuits, but also enhances the simulation of autonomous circuits. Due to the specific algorithm construction, this hierarchical preconditioning can be achieved by solving a set of linear matrix problems with tree-like data dependency. Hence, it can be naturally parallelized to further improve the simulation efficiency. An efficient parallel HB simulation engine has been developed by distributing the simulation workload over a cluster of machines via message passing interface (MPI). Our experiments have shown that this new parallel HB algorithm can achieve the significant runtime speedup over the conventional serial preconditioning technique.

In recent years, a large body of statistical static timing analysis and statistical circuit optimization techniques have emerged, providing important avenues to account for the increasing process variations in design. The realization of these statistical methods often demands the availability of statistical process variation models whose accuracy, however, is severely hampered by limitations in test structure design, test time and various sources of inaccuracy inevitably incurred in process characterization. Consequently, it is desired that statistical circuit analysis and optimization can be conducted based upon imprecise statistical variation models. In this paper, we present an efficient importance sampling based optimization framework that can translate the uncertainty in the process models to the uncertainty in parametric yield, thus offering the very much desired statistical best/worst-case circuit analysis capability accounting for unavoidable complexity in process characterization. Unlike the previously proposed statistical learning and probabilistic interval based techniques, our new technique efficiently computes tight bounds of the parametric circuit yields based upon bounds of statistical process model parameters while fully capturing correlation between various process variations. Furthermore, our new technique provides valuable guidance to process characterization. Examples are included to demonstrate the application of our general analysis framework under the context of statistical static timing analysis.

With the growing concern of process variability, parame- terized circuit models are becoming increasingly important for circuit design and verification. Although techniques exist to extract compact VCO phase macromodels, a direct parametrization of VCO macromodels over a large set of parametric variations not only results in highly complex models, but also leads to significantly high computational cost. In this paper, an efficient parameterized VCO phase model generation technique is presented to capture the impacts of statistical parametric variations. The model extraction cost of our approach is significantly reduced by exploiting circuit-specific parameter dimension reduction, which effectively reduces the parameter space dimension over which the phase model needs to be extracted. The application of parameter reduction is facilitated by a novel and fast time-domain sampling technique that provides the essential statistical correlation data. Our numerical experiments have shown that the proposed model generation approach is more efficient than brute-force parametric modeling while producing accurate parameterized phase models that can capture large range parametric variations.

As a widely adopted frequency-domain method, harmonic balance (HB) provides efficient steady-state circuit analysis for analog and RF circuits. The conventional matrix-implicit Krylov subspace technique with the block-diagonal (BD) preconditioner has made it possible to compute the steady-state responses of large-scale circuits. However, not all HB problems, particularly strongly nonlinear circuit problems, can be solved reliably or efficiently using the standard BD-preconditioning technique. In this paper, hierarchical HB methods are proposed wherein robust preconditioning is provided via solution of a set of approximate linearized HB problems of progressively smaller size across multiple levels of the problem hierarchy. These subproblems are constructed using the same matrix-implicit formulation to retain the memory efficiency of Krylov subspace methods. Moreover, the number of allocated Krylov subspace matrix solvers, hence the memory usage, is significantly reduced via a recently introduced solver-sharing technique. The efficiency of our hierarchical preconditioning technique is further improved by adopting a one-step correction to the standard BD preconditioner and a multigrid-motivated iterative scheme. It has been shown that the proposed approaches can achieve up to 10 runtime speedup over the popular BD preconditioner and robust convergence even for strongly nonlinear circuits for which the BD preconditioner fails to converge.