Complex VLSI SOCs are manufactured on large 300mm wafers. Individual SOCs can show significant spatial performance gradients in the order of 10% per 10mm. The traditional approach to handling this variation in STA tools is a margin look-up table indexed by the diagonal of the bounding box around the gates in a timing path. In this paper we propose a new approach based on the concept of the Center-of-Delay of a timing path. We justify this new approach theoretically for linear performance gradients and present experimental data that shows that the new approach is both safe, and significantly less pessimistic than the existing method.

Although innovations in manufacturing technology help in reducing variations, IC design variations are a fact of life. In addition to random variations, systematic stress induced variations are becoming increasingly important. This panel will bring the diverse views from academia, foundries, fabless and IDM communities to address various topics on next generation solutions for variability, with the main emphasis on design and architecture solutions. Specifically, this panel will discuss:• Would new architectures mitigate variability in 22nm and beyond?• Could design regularity effectively mitigate variability?• What design techniques can be used to minimize variability 'on-the-fly'?• What new techniques can be used for memories, register arrays and flip-flops?

A transversal equalizer with half Baud spaced taps in the center and extended with Baud spaced taps on both sides is presented. This hybrid equalizer combines the benefits of Baud spaced equalizers-like superior equalization of notches in the middle of the transmission band-and fractionally spaced equalizers, which have a superior performance when equalizing asymmetric notches in the slope of the transmission band, when the same number of coefficients are used. The hybrid equalizer offers a reduced sensitivity to sampling time changes and the ability to model the matched filter in the receiver as the fractionally spaced equalizer. The problem of tap-wandering, which is present in fractionally spaced equalizers, is reduced due to the reduced degree of freedom in the coefficient adjustment.

A processor for the adaptation of the coefficients in high throughput adaptive equalizers is presented. The accumulation operation-fundamental basis of the adaptation process-is split into two steps: A fine-grain carry-save accumulation with time sharing factor 2 collects the products of estimated error and input symbols over a block length of 16 input symbols and operates at twice the symbol rate, a master accumulator with time-sharing factor 32 collects the block-sums from 16 fine-grain accumulators, multiplies them with the adaptation constant and carries out the final vector merging operation, saturation, tap leakage and radix-4 Booth recording. Three steps to reduce the power consumption of the fine-grain accumulators is presented and evaluated for a 14-bit-wide accumulator: The suppression of one state of the redundant codes for the value "1" in the carry save digit alphabet i.e. (0, 1) or (1,0), reduces the power consumption by 5.5%; The redundancy-reduced digit alphabet can be exploited to reduce the transistor count of the following full adder by one third, resulting in a significant input capacity reduction which increases the maximum clock frequency by nearly 15% and achieves further reduction of power consumption of 2.7%. Finally an optimized sign extension logic reduces the capacitive load of the input sign bits by 70%, eliminates six of the full adders in the sign extension slices and increases the power reduction to 19.2%. The maximum clock frequency of the accumulator could be increased by 18% due to the reduced internal lends.