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Jeff Gibson

dblp:92/916 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation › simulation
architectural simulation
0.012000
FLASH vs. (Simulated) FLASH: Closing the Simulation Loop · ASPLOS 2000
Performance modeling and evaluation › system-level analysis › architecture evaluation
processor performance evaluation
0.012000
FLASH vs. (Simulated) FLASH: Closing the Simulation Loop · ASPLOS 2000

Methods — techniques the papers use, named apart from their topics

microbenchmarking · 0.0hardware gold-standard comparison · 0.0
YearPublicationVenuePosition
2000 FLASH vs. (Simulated) FLASH: Closing the Simulation Loop
abstract
Simulation is the primary method for evaluating computer systems during all phases of the design process. One significant problem with simulation is that it rarely models the system exactly, and quantifying the resulting simulator error can be difficult. More importantly, architects often assume without proof that although their simulator may make inaccurate absolute performance predictions, it will still accurately predict architectural trends.This paper studies the source and magnitude of error in a range of architectural simulators by comparing the simulated execution time of several applications and microbenchmarks to their execution time on the actual hardware being modeled. The existence of a hardware gold standard allows us to find, quantify, and fix simulator inaccuracies. We then use the simulators to predict architectural trends and analyze the sensitivity of the results to the simulator configuration. We find that most of our simulators predict trends accurately, as long as they model all of the important performance effects for the application in question. Unfortunately, it is difficult to know what these effects are without having a hardware reference, as they can be quite subtle. This calls into question the value, for architectural studies, of highly detailed simulators whose characteristics are not carefully validated against s real hardware design.
Jeff Gibson, Robert Kunz, David Ofelt, Mark A. Heinrich
ASPLOS1