Spatially distributed 3D circuit models are extracted with a segment-to-segment BEM (Boundary Element Method) algorithm for both capacitance and inverse inductance couplings rather than using the traditional net-to-net approach. Critical issues regarding the extraction efficiency and accuracy of segment-to-segment BEM capacitance models are explored. An adaptive discretization scheme is developed for segment-to-segment capacitance extraction and also applied to segment-to-segment high-frequency inverse inductance extraction. We demonstrate the limitations of the duality between capacitance and inverse inductance. Examples demonstrating the accuracy of these models are presented for real packaging cases.

We present a noise-driven effective capacitance method for estimating the combined propagation noise and crosstalk noise. Gate propagation noise rules are efficiently calculated inside the Ceff procedure to determine a linear Thevenin model of the victim driver. A voltage-dependent current source model [2, 6] of the driver, along with a load capacitor is analyzed to generate the gate output waveform, from which noise rules are directly extracted. This method removes potential errors introduced in traditional look-up table or fitted-equation based noise rules. The linear driver Thevenin model can then be employed to analyze the propagation noise, while the same Thevenin resistance can be used to analyze the crosstalk noise. The combined coupling and propagation noise can then be estimated using superposition. In this work, we extend the popular timing-driven effective capacitance method into the noise domain. Similar to the effective capacitance method in timing analysis, this technique can successfully separate the nonlinear driver analysis from the linear interconnect analysis. In addition, the linear driver model can significantly ease the task of finding the worst-case peak alignment among all the victim and aggressor noise sources. Experimental results on both RC and RLC nets from industry designs show both accuracy and efficiency compared to SPICE results.

One means of reducing pessimism in crosstalk analysis is to consider timing orthogonality. While earlier works have addressed the temporal alignment of timing windows [1, 2, 3, 4], these treatments have overlooked one key point. Crosstalk noise failures are frequency dependent. A chip that functions at one frequency can fail due to crosstalk noise at faster and slower frequencies. Moreover, because system developers and manufacturers need chips that operate over a wide range of frequencies, noise analysis tools should guarantee a wide range of operation. In this paper, we explain this phenomenon and propose a simple procedure to include timing information and guarantee functionality from dc to fmax.

Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of the magnetic couplings for final design verification can be a daunting task. In general, when modeling inductance and the associated return paths, one must consider the on-chip conductors as well as the system packaging. This can result in an RLC circuit size that is impractical for traditional simulators. In this paper we demonstrate a localized, window-based extraction and simulation methodology that employs the recently proposed susceptance (the inverse of inductance matrix) concept. We provide a qualitative explanation for the efficacy of this approach, and demonstrate how it facilitates pre-manufacturing simulations that would otherwise be intractable. A critical aspect of this simulation efficiency is owed to a susceptance-based circuit formation that we prove to be symmetric positive definite. This property, along with the sparsity of the susceptance matrix, enables the use of some advanced sparse matrix solvers. lye demonstrate this extraction and simulation methodology on some industrial examples.

HE appropriate interconnect model has changed several times over the past two decades due to aggressive technology scaling. New, more accurate interconnect models were introduced when parasitic effects that were negligible in earlier technologies, could no longer be ignored. Currently, RC models are used to analyze high resistance nets while capacitive models are used for less resistive interconnects. However, on-chip inductance is becoming increasingly important since integrated circuits now operate at frequencies where the inductive impedance of thick wide wires is comparable to wire resistance and line lengths are long enough, relative to signal rise times, for transmission line behavior to become significant. Furthermore, this trend shows every indication of spreading beyond the relatively few lines it now affects. Operating frequencies that have increased dramatically over the past decade, are expected to maintain the same rate of increase over the next decade approaching 10 GHz by the year 2012. The use of thick upper level metals, large die sizes, and low resistance copper interconnect—already used in many commercial CMOS technologies, will likewise continue. Finally, because large die sizes enable more system integration, the use of long thick wide wires, once largely devoted to global clock distribution networks, will spread to critical data-buses and control lines. This special issue deals with the design and analysis of integrated circuits including parasitic on-chip inductance. It does not deal with intentionally designed structures like the spiral inductors used in RF circuits and LC tank oscillators. As evidence that the subject material is still under investigation, the papers in this special issue do not present a unified approach to modeling parasitic inductance. The most notable difference centers around the use of 2-D (or loop inductance) models versus more general 3-D inductance models, and at the center of this debate is the question of current loops formed by return currents. The 3-D model advocates take the position that the return current paths are fundamentally unknown and present sophisticated analysis methods to cope with the increased complexity of 3-D models. The 2-D advocates insist that the return currents are equal and opposite to the interconnect currents and can therefore, employ simpler models. While this debate is apparent in the second paper which favors 2-D models and the third, fourth, and sixth papers which favor 3-D models, several other papers also imply a preference by presenting analytical methods that are suitable to 2-D models only. The paper summary below highlights when notable, the authors stated or implied preference to 2-D or 3-D models. In the first paper, Ismail presents several analytical methods for including inductive effects in both timing and noise analysis. The analytical models he presents are only applicable to

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.

This paper reviews the status of present day on-chip wiring design methodologies and understanding. A brief explanation is given of the fundamental transmission-line properties that should be considered for accurate prediction of crosstalk, common-mode noise and clock skew. The deficiencies of RC-circuit representation are highlighted and design guidelines are given for using modeling and simulation techniques that have been previously used for package interconnections. Such techniques are believed to teach designers how to make better use of available technologies and help them architect systems that operate with many-GHz clock rates.

To make three-dimensional (3-D) on-chip interconnect inductance extraction tractable, it is necessary to ignore parasitic couplings without compromising critical properties of the interconnect system. It is demonstrated that simply discarding faraway mutual inductance couplings can lead to an unstable approximate inductance matrix. In this paper, we describe an equipotential shell methodology, which generates a partial inductance matrix that is sparse yet stable and symmetric. We prove the positive definiteness of the resulting approximate inductance matrix when the equipotential shells are properly defined. Importantly, the equipotential shell approach also provably preserves the inductance of loops if they are enclosed entirely within the shells of their segments. Methods for sizing the shells to control the accuracy are presented. To demonstrate the overall efficacy for on-chip extraction, ellipsoid shells, which are a special case of the general equipotential shell approach, are presented and demonstrated for both on-chip and system-level extraction examples.

In this paper we present a generalization of popular linear model reduction methods, such as Lanczos- and Arnoldi-based algorithms based on rational approximation, to systems whose response to interesting external inputs can be described by a few terms in a functional series expansion such as a Volterra series. The approach allows automatic generation of macromodels that include frequency-dependent nonlinear effects.

It is well understood that frequency independent lumped-element circuits can be used to accurately model proximity and skin effects in transmission lines [7]. Furthermore, it is also understood that these circuits can be synthesized knowing only the high and the low frequency resistances and inductances [4]. Existing VLSI extraction tools however, are not efficient enough to solve for the frequency dependent resistances and inductances on large VLSI layouts, nor do they synthesize circuits suitable for timing analysis. We propose a rules-based method that efficiently and accurately captures the high and low frequency characteristics directly from layout shapes, and subsequently synthesizes a simple frequency independent ladder circuit suitable for timing analysis. We compare our results to other simulation results.

The design of system level interconnects to meet signal integrity objectives is a challenging problem. This paper formulates the transmission line synthesis problem as a constrained multidimensional optimization task for performance-driven routing of the complete net, taking into account factors like loading conditions on the line, loss in the line, and rise time of the input signal. Different design variables, such as width or resistivity of the interconnect, resistive source, or far-end termination, etc., can all be considered concurrently. A novel termination metric is described that is based upon forcing the impulse response waveform to be symmetric using the first three moments of the distributed system response. This metric provides an efficient means to trade off between signal rise time and ringing without requiring a time-domain simulation. Several examples are presented to demonstrate the efficacy of the proposed methodology.

Boundary element methods (BEM) are often used for complex 3-D capacitance extraction because of their efficiency, ease of data preparation, and automatic handling of open regions.BEM capacitance extraction, however, yields a dense set of linear equations that makes solving via direct matrix methods such as Gaussian elimination prohibitive for large problem sizes.Although iterative, multipole-accelerated techniques have produced dramatic improvements in BEM capacitance extraction, accurate sparse approximations of the electrostatic potential matrix are still desirable for the following reasons.First, the corresponding capacitance models are sufficient for a large number of analysis and design applications.Moreover, even when the utmost accuracy is required, sparse approximations can be used to precondition iterative solution methods.In this paper, we propose a definition of electrostatic potential that can be used to formulate sparse approximations of the electrostatic potential matrix in both uniform and multilayered planar dielectrics.Any degree of sparsity can be obtained, and unlike conventional techniques which discard the smallest matrix terms, these approximations are provably positive definite for the troublesome cases with a uniform dielectric and without a groundplane.

The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis.The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters.The only drawbacks to this delay metric are the uncertainty as to whether it is an optimistic or a pessimistic estimate, and the restriction to step response delay estimation.In this paper, we prove that the Elmore delay is an absolute upper bound on the 50% delay of an RC tree response.Moreover, we prove that this bound holds for input signals other than steps, and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases.A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response.The utility of this bound is for understanding the accuracy and the limitations of the Elmore delay metric as we use it for design automation.

RLC transmission line synthesis is a difficult problem because minimal net delay cannot be achieved or accurately predicted unless: 1) a termination scheme is chosen and properly implemented, and 2) output driver transition rates are constrained at or below the net's capability.This paper describes a method to concurrently find, for any RLC net, an optimal termination value, a maximum source transition rate, and an approximate net delay using the first few response moments.When optimal termination is accomplished and transition rates do not exceed the capabilities of the net, the resulting delay metrics are an interesting extension of the popular Elmore delay metric for RC interconnects.The task of physical RLC interconnect design is facilitated by the ease with which these first few moments are calculated for generalized RLC lines.

This paper proposes a definition of magnetic vector potential that can be used to evaluate sparse partial inductance matrices. Unlike the commonly applied procedure of discarding the smallest matrix terms, the proposed approach maintains accuracy at middle and high frequencies and is guaranteed to be positive definite for any degree of sparsity (thereby producing stable circuit solutions). While the proposed technique is strictly based upon potential theory (i.e. the invariance of potential differences on the zero potential reference choice), the technique is, nevertheless, presented and discussed in both circuit and magnetic terms. The conventional and the proposed sparse formulation techniques are contrasted in terms of eigenvalues and circuit simulation results on practical examples.

Physical interconnect introduces new challenges for parameter extraction and delay calculation for application specific electronic module (ASEM) design automation. Efficiency dictates the precharacterization of extracted electrical parameters in the same manner as application specific integrated circuits (ASICs). However, ASEM interconnect is dominated by frequency dependent LC propagation which makes precharacterization difficult for all possible configurations. Moreover, simulating the transient behavior of the ASEM interconnect for noise and delay analysis requires the combined use of a variety of models and techniques for efficiently handling lossy, low-loss, frequency dependent, and coupled transmission lines together with lumped parasitic elements. We propose to use conformal mapping to generate "abstracted" models for the electrical parameters of various RLC interconnect cross-sections, including the frequency dependence caused by ground plane proximity and skin effects. Along with precharacterized lumped parasitic elements and nonlinear driver and load models, these models are simulated using a generalized time-domain macromodeling approach that can combine different types of transmission line analysis in one simulation environment. An automatic selection mechanism is derived for determination of the best time-domain macromodel for a particular distributed segment.