Demo Data from VLDB 2026 / reviewers in the wild / expert
Jean Davies Lesser
dblp:93/1059
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1980
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 94% Integrated circuit design · 6% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › test generation › fault test generation
delay fault test generation |
0.0 | 1 | 1980 | An Experimental Delay Test Generator for LSI Logic · IEEE Trans. Computers 1980 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1980 | An Experimental Delay Test Generator for LSI Logic · IEEE Trans. Computers 1980 |
Electronic design automation › design optimization
power/timing optimization |
0.0 | 1 | 1977 | An experimental system for power/timing optimization of LSI chips · DAC 1977 |
Electronic design automation › hardware test
test coverage |
0.0 | 1 | 1980 | An Experimental Delay Test Generator for LSI Logic · IEEE Trans. Computers 1980 |
Methods — techniques the papers use, named apart from their topics
level sensitive scan design · 0.0d-algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1980 | An Experimental Delay Test Generator for LSI LogicabstractDelay testing is a test procedure to verify the timing performance of manufactured logic networks. When a level-sensitive scan design (LSSD) discipline is used, all networks are combinational. Appropriate test patterns are selected on the basis of certain theoretical criteria. These criteria are embodied in an experimental test generation program. The program has successfully produced sets of delay tests for large logic networks. The average coverage achieved by these tests faDs within 95.8 percent to 99.9 percent of optimal. Jean Davies Lesser, John J. Shedletsky |
IEEE Trans. Computers | 1 |
| 1977 | An experimental system for power/timing optimization of LSI chips
Barbara J. Agule, Jean Davies Lesser, Albert E. Ruehli, Peter K. Wolff Sr. |
DAC | 2 |