BELLMAC-32A is a single-chip fully 32-bit high-end microprocessor designed in 2.5-?m twin-tub CMOS technology. This paper describes the gate matrix layout of random control logic in BELLMAC-32A with top-down hierarchical design methodology. The gate matrix layout provided (1) parallel team layout efforts, (2) adaptability to evolving logic design with short turnaround time, (3) high packing density competitive with hand layout, (4) compatibility with computer-aided layout and verification tools, (5) capability to fine-tune circuits, and (6) technology updatability. It took 6.5 engineer-years to complete the layout of random control logic with 7000 transistors although the logic design was continuously evolving during the layout period. The average packing density of gate matrix layout was 1500 ?m2 per transistor in random logic and 840 ?m2 per transistor in data path. BELLMAC-32A had more-than-three times performance improvement over its 3.5 ?m technology prototype chip BELLMAC-32, in which random control logic was implemented with polycells.

Previously the gate matrix technique was used to lay out the RALU section of a CMOS 32-bit CPU chip. It took 1.2 Engineer-Years to complete the layout of the RALU that contained more than 20,000 transistors with multiple-bus structure. The average packing density was 840 μm2 per transistor in 2.5 μm design rules. Recently we have applied the gate matrix technique to lay out the highly complex "random control logic" of the CPU. With a well-structured layout strategy, the gate matrix layout provided (1) adaptability to evolving logic design with short turnaround times, (2) compatibility with computer aids in layout verification, (3) high packing density competitive with hand layout, and (4) compatibility with a team approach to layout. It took 6.5 Engineer-Years to complete the error-free layout of over 7,000 transistors although the logic design was continuously evolving during the layout period. More than half of the layout efforts were due to logic changes. The average packing density in the final layout of the random control logic was about 1,500 μm2 per transistor with 2.5 μm design rules.