This brief presents a reconfigurable multichannel noise-shaping (NS) SAR analog-to-digital converter (ADC) with crosstalk suppression. All nonmemory blocks are multiplexed among all channels assisted by the proposed timing control scheme, enabling reconfiguration with negligible power and hardware cost. A novel approach to determine the design parameters of nonideal loop filters is proposed, and a crosstalk suppressed multichannel fully passive loop filter is developed based on this method. A memoryless binary dynamic element matching (DEM) is also adopted to suppress the nonlinearity of each channel. The ADC achieves a typical SNDR of 77.49/72.17/66.62 dB with a 20-kHz bandwidth under one-/two-/four-channel modes, respectively, realizing typical Schreier FoMs of 169.54, 167.20, and 164.64 dB. Averaged interchannel crosstalks are −79.17 and −77.37 dB with −2.5-dBFS inputs in all input channels under two- and four-channel modes.

This paper presents a second-order passive noise-shaping SAR ADC for low-power receivers, aimed at reducing the power consumption of the anti-aliasing filter and input buffer to enhance energy efficiency. A self-synchronized asynchronous logic with system control and standby mode is proposed, allowing the ADC to maintain high energy efficiency across a wide sampling range of 80kHz to 20MHz. Additionally, a dynamic control logic for the splitting monotonic switching DAC is proposed. Fabricated using a 55nm CMOS process, the ADC occupies only 0.012mm2. Measurement results demonstrate that, at a supply voltage of 0.8V and an oversampling ratio (OSR) of 5, the ADC achieves an effective number of bits (ENOB) between 7.6 and 8 bits across the specified sampling rates. Power consumption scales linearly from 105nW to 18.47µW with frequency, offering an energy-efficient solution for low-power receivers.

This paper presents an ultra-low power 915 MHz Local Oscillator (LO) with adaptive frequency calibration algorithm for IoT Wake-Up Receivers (WURs). The proposed algorithm can adaptively adjust and minimize the calibration time of each bit oscillator tuning word (OTW) as well as the number of OTWs that require re-calibration after open-loop time. These two features help reducing the average LO power consumption by minimizing the closed-loop frequency calibration time. The duty cycle of the closed-loop time can also be adjusted flexibly to further reduce the average LO power consumption at a given frequency stability requirement. Fabricated in 40-nm CMOS, this proposed algorithm reduces the frequency calibration time from 108 μs to 42 μs, achieving a time reduction of 61%. An average LO power consumption of 93 μW at a 5% closed-loop time duty cycle is measured with a frequency accuracy of 120 ppm.

The battery-free and crystal-less nodes require energy-efficient radio, leading to the design of the ultra-low-power crystal-less receiver. The paper proposes a crystal-less receiver classification method for state-of-the-art works and presents a sub-1mW Class-Ab crystal-less receiver architecture with a carrier-auxiliary intermediate frequency (IF) negative feedback local oscillator (LO) generator and approximate low-IF mode. The proposed LO generator and receiver are implemented using 55nm CMOS technology with a total power of 492.4µW. Without any crystals, the LO frequency based on the bulk acoustic wave (BAW) oscillator maintains a ±6ppm error range from 0°C to 70°C. After locking the LO calibration loop, the phase noise at the 1MHz offset is better than -137dBc/Hz and long-term frequency drift is less than ±0.06ppm in two seconds.

Ambient Internet of Things (IoT), with its low-cost and battery-free characteristics, holds substantial promise for future green IoT. However, such characteristics usually impose a strict constraint on the adopted radio frequency (RF) devices, resulting in undesirable RF link. One of the most important issues is carrier frequency offset (CFO), which adversely affects communication reliability. Noticing the signal sparsity in frequency domain, compressed sensing (CS) provides potential solutions to CFO estimation. In this paper, we decompose CFO into on-grid frequency and off-grid deviation, based on which two estimation algorithms are derived. In particular, the fast maximum likelihood-approximate message passing (FML-AMP) algorithm estimates the off-grid deviation with maximum likelihood estimator (MLE) and the on-grid frequency with AMP algorithm. The key is the derivation of the closed-form marginal distribution of the off-grid deviation, which enables the fast implementation of MLE and so facilitates the design of FML-AMP. To reduce complexity, a Newtonized orthogonal matching pursuit (NOMP) algorithm is further designed, which alternately applies Newton's method to estimate the off-grid deviation and orthogonal matching pursuit (OMP) to estimate the on-grid frequency. Numerical results demonstrate that both algorithms outperform existing methods and approach the Cramér-Rao bound at medium to high signal-to-noise ratio (SNR) regime.

This paper presents a novel high-sensitivity high-efficiency radio frequency (RF) energy harvester with a burst charging technology. The popular high-sensitivity scheme is increasing the number of RF rectifier’s stages to output higher voltage which is suitable to supply downstream electronics. This will reduce the input signal amplitude and power conversion efficiency (PCE), which in turn needs more stages and is thus lost in a vicious circle. This paper uses an optimal-stage high-efficiency RF rectifier to solve this problem. A low-frequency (LF) charge pump (CP) is cascaded with the rectifier to raise the DC voltage. To further improve the sensitivity, the system uses a burst charging mode to remove the charge pump’s loading effect on the RF rectifier. Measurements demonstrate a -31 dBm sensitivity for 1 V output across a capacitive load in a 55 nm CMOS process technology. The power conversion efficiency equals 31.3% at -25 dBm.

This paper presents a cold-start architecture for the boost converter at 54 mV in thermoelectric energy harvesting. Conventionally, a series of charge pump stages and huge area of pumping capacitors are typically used to generate a high voltage at a specific load current from an ultra-low TEG voltage source. Therefore, the proposed architecture employs a cascade structure of two capacitive voltage multipliers to realize start-up with fewer charge pump stages and on-chip pumping capacitance by the proposed burst charging mode. Powered by the output of the primary voltage multiplier, a strobe generator with ultra-low current consumption of 57 pA assists the inductive boost converter to start up by a one-shot strobe mechanism. Designed and simulated in a 55-nm CMOS process, the proposed cold-start scheme assists an inductive boost converter to self-start with a minimal TEG voltage of 54 mV in 41 ms while employing only 10 stages of charge pump and 146 pF pumping capacitors overall.

This paper presents an energy-efficient calibration-free hybrid noise-shaping SAR ADC for low-power high-resolution applications. A high-efficiency 2nd-order fully- passive noise-shaping technique is adopted in this circuit to achieve higher in-band noise attenuation for a better signal-to-noise ratio (SNR). Mismatch error shaping with digital prediction is used to mitigate harmonic distortions without affecting ADC's dynamic range, therefore greatly improving the signal-to-noise-and-distortion ratio (SNDR) and spurious- free dynamic range (SFDR). The prototype ADC is designed in 55 nm CMOS and occupies an area of 0.126 mm2. It consumes 7.426 μW at 400 kS/s sampling rate from a 1 V supply. The post-layout simulated SNDR is 91.05 dB for a 6.25 kHz bandwidth without any calibration, resulting in a Schreier figure of merit (FoMS) of 180.30 dB and a Walden figure of merit (FoMW) of 20.40 fJ/conversion-step.

Backscatter sensing with battery-less tag sensors has gained popularity in low-cost wireless sensing for IoT applications. This paper proposes a backscatter sensing method with a single tag for canceling the effect of path variation (PV), such as unknown reader-sensor distance and orientation. A reference/sensing (Ref/Sen) mode selection in the tag sensor is applied to generate the differential backscattered signals, which selects a reference/sensing capacitor by a mode-selection switch and causes the reflection coefficient variation. A Ref-Sen differential (RSD) variable ∆r is defined and calculated by the interrogator based on two signal parameters: power and phase. ∆r is a PV-independent variable corresponding to the sensing information. An RFID sensing system with a liquid-level tag sensor has been designed and evaluated. Experimental results demonstrate a 0.5-mm resolution in liquid-level sensing. The robustness-test results under different PVs, including 18 dBm power variation and 0.6 m distance variation, have proved the proposed PV-cancelling method’s validity. The standard deviations for the amplitude and phase variations are 0.00344 and 1.65°.

This paper presents an analog low-power sub-sampling phase locked loop (PLL) that tackles the reference spur caused by VCO load modulation from the sub-sampling operation. A complete analysis on the binary frequency shift keying (BFSK) effect including the impact of the VCO buffer is provided, followed by practical design guide that achieves the optimum spur/jitter trade-off. The proposed sub-sampling phase detector incorporates an active primary-secondary architecture for improved isolation to suppress the load modulation. The adaptive frequency locked loop (FLL) consumes zero power in the locked state and activates itself once unlocking is detected. The sub-sampling PLL is fabricated in a 40nm CMOS process. It achieves -121.5dBc/Hz phase noise at 1MHz offset frequency and an RMS jitter of 185fs integrated from 10k to 10MHz. The power dissipation is 1.14mW at 0.95V supply with a -254.1dB figure-of-merit. The proposed phase detector results in -73dBc reference spur that is among the lowest in state-of-art works.

This article introduces a highly integrated passive wireless sensing system based on the extended electronic product code (EPC) Gen2 protocol, using sensor tags and a reader to support concurrent data streams from multiple sensors. Multiple subcarrier multiple access (MSMA) is used by assigning different subcarrier frequencies to the sensor tags for backscattering so that each tag has an independent channel for communication to achieve the simultaneous streaming of multisensor data. In order to improve the subcarrier frequency accuracy and further increase the number of communication channels, this article proposes a novel method of subcarrier frequency calibration based on the Gen2 protocol. This method enables a high-accuracy clock to be generated on-chip. At the same time, this article also proposes a method based on Gen2 protocol to start a group of tags and receive real-time data in parallel. The tag chip is fabricated in a$0.18{-}\mu \text{m}$CMOS process with a die size of$850\,\,\mu \text{m}\,\,\times 850\,\,\mu \text{m}$, and the reader prototype is built using software-defined radio equipment. The test results show that the sensing system proposed in this article can collect and recognize concurrent data streams from multiple sensor tags synchronously. The measured sensitivity of the sensor tag is −14.9 dBm with a 3-axis accelerating sensor, and the calibration accuracy of subcarrier frequency is better than${\pm }{\mathrm {0.385}}$kHz in the range of 40–640 kHz. With this accuracy, the tags can be allocated up to 78 subcarrier communication channels theoretically.

In this paper, the analysis and design of a 57-64 CMOS Power Amplifier is discussed. The power-combining technique and the capacitor neutralization technique are applied to boost the performance of the purposed PA. The PA is designed in 65nm bulk CMOS process to achieve a saturated output power of 19.4dBm and a peak power-added efficiency of 22%. The power amplifier consumes 300mW from a 1.2V power supply at the output-refereed 1dB compression point of 16.1dBm, and the corresponding power-added efficiency is 13.0%. The passive devices, such as the transformers, the power-combiner and the pads, are designed by Electromagnetic Field Simulation on ADS momentum.

This paper presents a novel self-bias CMOS rectifier for ultra-high frequency (UHF) RF energy harvester, which achieves a high power conversion efficiency (PCE) at an ultra-low input power. Compared to other state-of-the-art topologies, the proposed architecture combines static and dynamic compensated techniques to enhance the conduction capacity when the input power is lower than -27dBm. A six- stage rectifier is designed using this proposed topology in a 130nm CMOS process technology. Operating at 915MHz and driving a 1MΩ load resistor, the post-layout simulation PCE of this work is 27.6% at -30dBm input power. A sensitivity of - 30dBm is stimulated with 0.8V output voltage across a capacitive load.

A charge pump circuit with two feedback loops and a reference current source is proposed. It adopts the replica technique to minimize current mismatch and variation over a wide output range. One feedback loop is used to cancel mismatch between charging and discharging currents in order to minimize PLL reference spur and static phase offset. The other feedback loop stabilizes the current at the design value in different corners by replicating the reference current, which is from a low temperature drift current source. The proposed charge pump circuit with dual feedback loops achieves lower than 0.01% current mismatch, and less than 0.015% current variation over the output voltage range from 0.2 V to 1.0V in the 55 nm CMOS process with 1.2 V supply.

A novel type of highly efficient conditional feedthrough pulse-triggered flip-flop (P-FF) is proposed and demonstrated. The data-to-output (D-to-Q) delay in this circuit was highly optimized using predischarging and conditional signal feedthrough schemes. Power consumption was also reduced using a shared pulse generator and an output feedback-controlled conditional keeper, which diminished the floating status of the internal node. The driving strength of this design was further enhanced by including an additional pull-down path at the output node. Various postlayout simulation results applied to 16-nm FinFET technology demonstrated a higher energy efficiency (at all input data toggle rates) for the proposed topology than comparable P-FF devices. Notably, the proposed model achieved a 62% D-to-Q delay reduction, compared to a transmission gate FF, outperforming the device by more than 66% in terms of power efficiency and 87% in energy efficiency (at a 50% input data toggle rate). Improvements were even more significant in comparison with other conventional P-FFs. These results suggest the proposed design to be a viable new option for high-efficiency sequential elements in high-speed applications.

In this paper, we present a novel high-throughput anti-collision algorithm for passive ultrahigh-frequency (UHF) radio-frequency identification (RFID) systems. Our algorithm utilizes signal recovery techniques of collided tag signals to both recover tag communications and obtain an accurate count of all tags in the field. Passive UHF RFID systems are used for long-range passive communications for applications including supply chain management and electronic tolling. Anti-collision algorithms are used to ensure successful RFID tag communications due to the likelihood of multiple tags being in the field and attempting to communicate simultaneously. The limited on-tag functionality necessitates the use of simple anti-collision algorithms such as a dynamic frame slotted Aloha (DFSA) algorithm. With our novel collision detection and signal recovery anti-collision algorithm, the RFID reader can retrieve multiple valid communications from each collided slot in a DFSA-based anti-collision protocol, while our algorithm allocates an optimal number of slots resulting in more collided but recoverable slots and fewer empty slots. Our algorithm achieves a nearly 100% throughput improvement with an expected throughput of 0.85 compared with an expected throughput of 0.426 for a standard DFSA algorithm. The reader receiver with the proposed algorithm is implemented in a field-programmable gate array and the whole reader system is verified using the communication tests with commercial tags. According to the synthesized results in an SMIC 0.13-$\mu \text{m}$CMOS technology, the collision detection and signal recovery module consumes about 135k GE.Note to Practitioners—Signal recovery methods are capable of extracting information from collided signals. In this paper, we introduce and analyze a signal recovery method based on the voltage histogram of the received signal. Both the original signals and the number of collided signals are recovered. The information of tags is used by our novel algorithm to increase the system throughput in DFSA-based anti-collision algorithms. The recovered signals allow our algorithm to directly obtain the tag identifier. By determining the number of collided signals, our algorithm is able to calculate an accurate estimate of the total number of tags in the reader’s field. With signal recovery and an accurate tag count, our algorithm is able to reduce the total number of slots needed to identify all tags, thereby increasing the throughput. We present a novel frame length optimization method that increases throughout by shrinking the number of slots, thereby intentionally causing collisions and reducing the total number of empty slots. In addition, we present a hardware implementation of our novel method that is suitable for integration into RFID readers. When the signal strengths of the tags in collision in the in-phase or quadrature path are not close to each other, the performance of our method is much better than that of the traditional method in which the collision signal is treated as ineffective and ignored.

A low power receiver with impedance transparent RF front end is presented. By using the 4‐path passive mixer and the active feedback of LNA, the baseband impedance profile is further transferred to receiver input. While a LO‐defined input matching is formed by RF front end, the linearity of entire receiver chain is improved. Furthermore, derivative superposition technique is employed to cancel the distortion of the CMOS LNA. A 3rd‐order active‐RC filter is designed with current‐efficient feedforward compensated OTA. And a digital‐to‐time converter (DTC) assisted fractional‐N all‐digital phase‐locked loop (ADPLL) is codesigned with receiver to meet the IoT requirements. The presented receiver is fabricated in 55 nm CMOS technology with an active area of 2.3 mm2 and power consumption of 20 mW. Measurement results show that the receiver achieves 5.3 dB NF with 78 dB gain from 0.6 to 1 GHz, the RX out‐of‐band IIP3 is +8 dBm, and in‐band IIP3 is −10 dBm, and the ADPLL achieves −94 dBc/Hz in‐band PN and −120.5 dBc/Hz at 1 MHz offset.

This paper implements a complementary Class‐C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start‐up with low power consumption. By optimizing three switched capacitor arrays and employing fractional capacitor array with sigma‐delta modulator (SDM), the presented DCO operates from 3.22 GHz to 5.45 GHz with a 51.5% frequency tuning range and 0.1 ppm frequency resolution. The design was implemented in a 65 nm CMOS process with power consumption of 2.8 mA at 1.2 V voltage supply. Measurement results show that the phase noise is about −126 dBc/Hz at 3 MHz offset from a 5.054 GHz carrier frequency with the 1/f3 corner frequency of 260 KHz. The resulting FoMT achieves 199.4 dBc/Hz and varies less than 2 dB across the frequency tuning range.

This paper presents a wirelessly powered implantable electrochemical sensor tag for continuous blood glucose monitoring. The system is remotely powered by a 13.56-MHz inductive link and utilizes an ISO 15693 radio frequency identification (RFID) standard for communication. This paper provides reliable and accurate measurement for changing glucose level. The sensor tag employs a long-term glucose sensor, a winding ferrite antenna, an RFID front-end, a potentiostat, a 10-bit sigma-delta analog to digital converter, an on-chip temperature sensor, and a digital baseband for protocol processing and control. A high-frequency external reader is used to power, command, and configure the sensor tag. The only off-chip support circuitry required is a tuned antenna and a glucose microsensor. The integrated chip fabricated in SMIC 0.13-μm CMOS process occupies an area of 1.2 mm ×2 mm and consumes 50 μW. The power sensitivity of the whole system is -4 dBm. The sensor tag achieves a measured glucose range of 0-30 mM with a sensitivity of 0.75 nA/mM.

A low-noise triple band transmitter for GSM triple-band and WCDMA is presented. By programming parameters, analog baseband and RF frontend can handle signals of different protocols and frequency bands. Novel linearization method is used in LPF and driver amplifier to meet the demand of 3G systems. Noise optimization is also adopted so that our transmitter achieves −157 dBc/Hz noise at 190 MHz frequency offset in WCDMA band, which eliminates external SAW filter.

A creative dynamic frequency scaling method in contactless smart card is presented for the first time. A low power magnetic field detection circuit, a simple load detection circuit, the quick load comparator and the simple clock switch scheme in the method are also presented. The test result shows that the longest communication distance is improved from 6 to 8 cm compared to the same contactless smart card (CSC) chip using the fixed frequency divided by 4 and the transaction time is saved by 18% in average, compared to the same CSC chip using the fixed frequency divided by 8.

A fully differential charge pump is proposed in this paper. It adopts the replica technique to eliminate the effect of channel-length modulation, and the charging and discharging currents can match well in a wide output range. A rail-to-rail common-mode feedback circuit is employed to ensure the large swing of the charge pump unrestricted. The charge pump is designed and fabricated in SMIC 0.18μm CMOS process. The measured reference spur-level is about −73dBc and the in-band phase noise is nearly −90dBc/Hz@1KHz. The power dissipation of the charge pump is only 1mW.

A new architecture of UHF (ultra high frequency) RFID (radio frequency identification) digital receiver for SoC (system-on-chip) implementation is presented in this paper. For the system requirements, the design uses a unique two-stage correlation algorithm to estimate the frequency of the received data which may have large frequency deviation and also to achieve fast data decoding. Considering the single chip integration, we optimize the implementation for both low hardware cost and quick response. The function of the design is verified through FPGA implementation on Altera StratixII EP2S60 with great performance and its chip design used the SMIC 0.18mum process along with other parts of the UHF RFID interrogator chip.

A high performance digital demodulator for RFID reader receiver is proposed. After carefully analyzing the characteristics of the received data, correlation operation is introduced into the demodulator to estimate the frequency of the received data and decode them. Simulation result indicates that this demodulator can work well under the 6dB input signal-to-noise ratio (SNR) with +/- 22% frequency deviation tolerance. FPGA implementation result shows that the communication distance between reader and tag can be extended to 5m above by the use of this demodulator.

This paper presents a novel synchronization technique with adaptive mode detection feature for the DVB-H system. The proposed joint algorithm doesn't depend on the knowledge of the cyclic prefix length to accomplish the maximum likelihood correlation sum, compared with the conventional algorithm. A reliable adaptive mode detection scheme, including DFT points and cyclic prefix length detection, is also presented. It exploits the periodic character of the continuous correlation sum function as the decision criteria. In the frequency selective fading channel, this approach not only shortens the blind synchronization times but also reduces the implementation complexity by 91.3%

No abstract available.

An accurate 1.08-GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process. In this paper we present a new convenient method of calculation of oscillating period. With this period calculation technique, the frequency tuning curves agree perfectly with the experiment. At a 3.3-V supply, the LC-VCO measures a phase noise of -82.2 dBc/Hz at a 10kHz frequency offset while dissipating 3.1mA current. Chip size is 0.86mm x 0.82mm.

This paper describes a new prediction method of tuning curves of a LC-tank voltage-controlled oscillator (VCO) with period calculation technique. With this period calculation technique, the prediction of oscillator tuning curves is more accurate compared with the traditional harmonic approximation. The theoretical analyses are experimentally validated with a CMOS complementary LC-tank VCO implemented in 0.35/spl mu/m 1P4M pure logic CMOS process.

For low-cost RFID systems, the design of passive tags is a key issue in anti-collision protocols where lower power consumption allows a longer working distance between tags and the reader. In this paper, we look at anti-collision protocols in tags ’ processing for their power optimization. We propose a new criterion, which takes into account both energy consumption and time complexity, to evaluate anti-collision protocols. An improved protocol is also presented for power savings.

The discrete wavelet transform (DWT) has received considerable attention in the context of image processing due to its temporal and frequency characteristics. A specific VLSI architecture for the forward/inverse DWT is presented. The characteristics of the structure and coefficients are utilized to reduce the circuit area. In addition, the Booth algorithm and balanced pipelines have been adopted which result in a high throughput at 2 outputs per clock and 5 clocks' pipeline latency. This design described and verified by the VHDL is synthesized by the Synopsys synthesizer. The synthesis results show that the gate-level circuit contains 5058 gates and the throughput can reach 110 M points/s when LSI 10 K CMOS technology is used.