This work introduces a novel security framework for wireless sensor networks (WSN) based on dynamic duty cycle, which allows nodes to detect their compromised neighbors based on unanticipated fluctuations in network traffic send rate over time. Our framework was assessed by its ability to detect advanced WSN threats (e.g., active, passive, or both attacks). One of the benefits of this framework is that it reduces all threats to unanticipated power dissipation. In other words, the framework assumes any neighbor not conforming to predicted power levels has been communicating with an unauthorized node, and thus is compromised. This threat model is emulated by applying pseudo random but bound (large to small) power dissipations to arbitrary nodes. Simulation results demonstrated that this framework was effective in detecting and isolating compromised sensor nodes.

Microarray images when contaminated with noise may severely affect the detection and quantification of gene expression. In this paper, we propose to use the complex Gaussian scale mixture (CGSM) model in complex wavelet domain for noise reduction in complementary DNA microarray images. Based on the joint information in the red and green channel microarray images, we model the complex wavelet coefficients of the channel images jointly using the CGSM, and subsequently perform image denoising using Bayes least square estimator in complex wavelet domain. The experimental results show that using the CGSM of complex wavelet coefficients provides better noise reduction of microarray images compared to other complex wavelet-based models.

The development of energy-conscious embedded and/or mobile systems exposes a trade-off between energy consumption and system performance. Recent microprocessors have incorporated dynamic voltage scaling as a tool that system software can use to explore this trade-off. Developing appropriate heuristics to control this feature is a non-trivial venture; as has been shown in the past, voltage-scaling heuristics that closely track perceived performance requirements do not save much energy, while those that save the most energy tend to do so at the expense of performance resulting in poor response time, for example. We note that the task of dynamically scaling processor speed and voltage to meet changing performance requirements resembles a classical control-systems problem, and so we apply a bit of control theory to the task in order to define a new voltage-scaling algorithm. We find that, using our nqPID (not quite PID) algorithm, one can improve upon the current best-of-class heuristic Pering's AVGN algorithm, based on Govil's AGED AVERAGES algorithm and Weiser's PAST algorithm in both energy consumption and performance. The study is execution-based, not-trace-based; the voltage-scaling heuristics were integrated into an embedded operating system running on a Motorola M-CORE processor model. The applications studied are all members of the MediaBench benchmark suite.

Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM latency and bandwidth and diminishing returns of increasing superscalar ILP and cache sizes have led to the proposal of new microprocessor architectures that implement processor-in- memory, stream processing, and tiled processing. Each architecture is typically evaluated separately and compared to a baseline architecture. In this paper, we evaluate the performance of processors that implement these architectures on a common set of signal processing kernels.The implementation results are compared with the measured performance of a conventional system based on the PowerPC with Altivec. The results show that these new processors show significant improvements over conventional systems and that each architecture has its own strengths and weaknesses.