Demo Data from VLDB 2026 / reviewers in the wild / expert
Kathy Dang Nguyen
dblp:93/3314
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 59% Embedded and real-time systems · 41% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
system-level design |
0.1 | 2 | 2007 | A UML-Based Design Framework for Time-Triggered Applications · RTSS 2007 Model-Driven SoC Design via Executable UML to SystemC · RTSS 2004 |
Embedded and real-time systems › real-time embedded systems › time-triggered systems
time-triggered architecture |
0.1 | 1 | 2007 | A UML-Based Design Framework for Time-Triggered Applications · RTSS 2007 |
Embedded and real-time systems
model-based design |
0.0 | 1 | 2004 | Model-Driven SoC Design via Executable UML to SystemC · RTSS 2004 |
Electronic design automation
hardware verification and test |
0.0 | 2 | 2007 | A UML-Based Design Framework for Time-Triggered Applications · RTSS 2007 Model-Driven SoC Design via Executable UML to SystemC · RTSS 2004 |
Electronic design automation › hardware verification and test › design validation
functional validation |
0.0 | 1 | 2004 | Model-Driven SoC Design via Executable UML to SystemC · RTSS 2004 |
Methods — techniques the papers use, named apart from their topics
systemc · 0.1UML · 0.1rhapsody · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | A UML-Based Design Framework for Time-Triggered ApplicationsabstractTime-triggered architectures (TTAs) are strong candidate platforms for safety-critical real-time applications. A typical time-triggered architecture is constituted by one or more clusters. Each cluster consists of nodes communicating with one another via a time-triggered communication protocol. Designing applications to run on such a platform is a challenging task. We address this problem by constructing a UML-based design framework which exposes the essential features of the time-triggered platforms at the UML-level and allows applications to be developed at a more abstract level before full implementation. To support preliminary functional validation, we have constructed a translator by which SystemC code can be automatically generated from UML designs. Our framework enables fast prototyping of time-triggered applications and early design validation. It also supports key design principles of TTAs, such as temporal firewalls and composability. Kathy Dang Nguyen, P. S. Thiagarajan, Weng-Fai Wong |
RTSS | 1 |
| 2004 | Model-Driven SoC Design via Executable UML to SystemCabstractWe present a system level description mechanism based on UML-notations from which one can automatically extract SystemC code. Our modelling framework is based on a restricted set of UML diagram types and some standard extensions influenced by the communication infrastructure of SystemC. The system specifications are developed using the UML-compatible tool, Rhapsody (2004). We then translate the internal representation of the design generated by Rhapsody into SystemC code. The extensions we have implemented using the stereotype feature of the Rhapsody tool pull up the communication infrastructure and timing features of SystemC to the UML-level. Consequently, we can describe executable platforms at the UML-level as well as translate UML-based application descriptions to SystemC level. Kathy Dang Nguyen, Zhenxin Sun, P. S. Thiagarajan, Weng-Fai Wong |
RTSS | 1 |