The need for faster and more reliable yield ramp-up when introducing new CMOS technologies is driving the effort to acquire and analyze valuable information from production test, for the process of identification of yield detractors. This paper addresses a key step in the phase of "industrialization" of these processes: standardization. The objective of standardization is to enable a seamless flow for production integrated scan diagnosis in a multi-tool, multi-vendor environment. To make analysis of chips failing the production test more efficient, a process flow and a file format to store the failing response of the chips is proposed. This enables a smooth exchange of production test data from ATE to diagnosis, failure analysis, design and process

This paper discusses the challenges associated with diagnosing chain integrity and system logic failures in the production test environment with limited failure information. The following three methods were proposed to enhance diagnosis resolution in this scenario: (1) static pattern re-ordering (2) dynamic pattern re-ordering (3) per-pin based diagnosis. Experimental results illustrate that per-pin based failure logging and diagnosis algorithms enable scan chain diagnosis in volume production environment. Successful application of per-pin based chain diagnosis is demonstrated with an industrial case

This paper presents a flow for using logic diagnosis to turn production material into vehicles for yield learning. High throughput logic diagnosis is combined with the newly emerging field of design for manufacturing to enable layout aware diagnosis. The ability of the flow to calculate feature failure rates and the application of the failure rates for yield learning is demonstrated through volume data analysis on a production ASIC

As electronic design feature sizes continue to shrink and clock speeds continue to rise, more and more companies have turned to at-speed test techniques to help ensure high test and product quality. Due to incomplete timing information during automatic test pattern generation (ATPG), it is possible that some at-speed patterns may activate paths which are not required to meet system speed, and these patterns may fail during production test. It is often difficult and time consuming to identify these paths manually. This paper describes how to use diagnosis techniques to automatically identify these paths. Using this approach, the authors found most of these paths were false or multicycle paths inside DFT logic. These could be fixed by enhancing the timing exception paths used during ATPG to mask out transition values through these paths. Elimination of these paths resulted in a 300 MHz increase in the speed of the transition fault test pattern. However, occasionally the authors did find some failing paths were real functional problems and design changes were needed to resolve them

Diagnosis of scan test fail data plays a crucial role in enhancing ramp up of new CMOS technology generations. To enable faster feedback it is preferable to establish a monitoring diagnosis methodology on the production test floor. This paper reports result of a study on using test time optimized compressed scan technology and associated new algorithms for fault diagnosis. Data is based on a system-on-a-chip (SoC) product that is manufactured using Infineon Technologies' 130 nm process. A comparison with uncompressed scan test and diagnosis shows feasibility of implementing a monitoring diagnosis flow with compressed scan test serving the high throughput test flow.

With the continuous drive to smaller features, introduction of new manufacturing materials, sub-wavelength lithography, and process and design interaction, achieving acceptable yield at technology nodes 130 nm and below is proving to be a daunting task. At these technology nodes yield is limited not just by random defects but also increasingly by systematic yield detracting mechanisms. In addition, a larger portion of the defects are becoming non-visual and/or parametric in nature. In fact many defects that cause electrical failures are not detectable by the traditional defect sourcing techniques such as inline inspection.

In scan test environment, designs with embedded compression techniques can achieve dramatic reduction in test data volume and test application time. However, performing fault diagnosis with the reduced test data becomes a challenge. In this paper, we provide a general methodology based on circuit transformation technique that can be applied for performing fault diagnosis in the context of any compression technique. The proposed methodology enables seamless reuse of the existing standard ATPG based diagnosis infrastructure with compressed test data. Experimental results indicate that the diagnostic resolution of devices with embedded compression is comparable with that of devices without embedded compression.

This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizing the coverage of node-to-node bridging defects. Volume data obtained by testing a production ASIC with these new multiple-detect patterns shows increased defect screening capability and very good agreement with the bridging coverage estimated by the ATPG tool. 1.

This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

This paper presents novel systematic design techniques for the automated register transfer level synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by pseudorandom test pattern generators driving parallel scan chains. Using a concept of linear feedback shift register (LFSR) duality this paper relates the logical states of LFSRs and circuits spacing their inputs to each of the output channels. Consequently, the method generates a phase-shifter network satisfying criteria of channel separation and circuit complexity by taking advantage of simple logic simulation of the LFSRs. It is shown that it is possible to synthesize in a time-efficient manner very large and fast phase shifters for built-in self-test applications with guaranteed minimum phaseshifts between scan chains, and very low delay and area of virtually one two-way XOR gate/channel.

This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200 K to 800 K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST controller for at-speed testing. Comparative data on fault grades and area overhead between automatic test pattern generation (ATPG) and logic BIST are reported. The experimental results demonstrate that with automation of the proposed solutions, logic BIST can achieve test quality approaching that of ATPG with minimal area overhead and few changes to the design flow.

The paper introduces a new algorithm for the automated synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by two-dimensional test generators. The algorithms presented in the paper synthesize in a time-efficient manner very large and fast phase shifters for built in self-test environment, with guaranteed minimal phase shifts between scan chains, and very low delay and area of virtually one 2-way XOR gate per channel.

This paper presents a novel test point insertion technique which, unlike the previous ones, is based on a constructive methodology. A divide and conquer approach is used to partition the entire test into multiple phases. In each phase a group of test points targeting a specific set of faults is selected. Control points within a particular phase are enabled by fixed values, resulting in a simple and natural sharing of the logic driving them. Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases.