Dynamic graphs are ubiquitous in real-world scenarios, demanding both timely updates and low-latency responses. However, existing FPGA-based solutions still face three major limitations in supporting such workloads: • Heavy CPU dependence [3] • Inadequate support for dynamic graphs [1] , [2] • Poor support for irregular updates [4]

Industrial information transmitted through data centers (DCs) is increasingly exposed to more widespread and powerful attack threats. In this article, we propose a chaotic encryption scheme that utilizes a reversible hybrid evolution life-like cellular automata (CA) and 4D modulation to enhance industrial information security. A chaotic permutation based on the logistic-adjusted-sine map and 4D modulation is applied. Subsequently, the rule selection method of the life-like CA is optimized. The reversible hybrid evolution life-like CA is used for block data diffusion, and a bidirectional diffusion mechanism is designed for the block diffusion. Finally, the 4D encrypted data with a bit rate of 224 Gb/s has been successfully verified over an 80 km standard single-mode fiber. The results indicate that the proposed encryption scheme demonstrates strong resistance to cryptanalytical attacks. Attackers cannot obtain valid data when the optical signal-to-noise ratio of the eavesdropping channel is below 18 dB. This scheme provides robust security guarantees for industrial information transmission in DCs.

We propose an electrostatics-based placement algorithm for large-scale mixed-size circuits (ePlace-MS). ePlace-MS is generalized, flat, analytic and nonlinear. The density modeling method eDensity is extended to handle the mixed-size placement. We conduct detailed analysis on the correctness of the gradient formulation and the numerical solution, as well as the rationale of dc removal and the advantages over prior density functions. Nesterov's method is used as the nonlinear solver, which shows high yet stable performance over mixed-size circuits. The steplength is set as the inverse of Lipschitz constant of the gradient function, while we develop a backtracking method to prevent overestimation. An approximated nonlinear preconditioner is developed to minimize the topological and physical differences between large macros and standard cells. Besides, we devise a simulated annealer to legalize the layout of macros and use a second-phase global placement to reoptimize the standard cell layout. All the above innovations are integrated into our mixed-size placement prototype ePlace-MS, which outperforms all the related works in literature with better quality and efficiency. Compared to the leading-edge mixed-size placer NTUplace3, ePlace-MS produces up to 22.98% and on average 8.22% shorter wirelength over all the 16 modern mixed-size benchmark circuits with the same runtime.

In this paper, we studied the semantic consistency maintenance issue between heterogeneous contexts, that is, how a firm ‟ busi-ness process of one e-marketplace can be transformed to another firm‟s business process of another e-marketplace in a semantically consistent way. The proposed solution of this paper uses XML Product Map (XPM) of collaborative concept to represent semantically consistent business processes, and adopts common action concept pool and XPM documents to design heterogeneous business processes that are suitable for heterogeneous business process transformation. We motivated the approach with a real-world PVC poncho trade problem and explained it in architecture of collaborative process design and automatic service provision. We reported the implementation specification within a hybrid human-agent framework, where four layers of system modules are specified. The approach is evaluated based on a new semantic impact chain method particularly for evaluating concept consistency in meaning representation between heterogeneous contexts of business processes.

W e implement and experiment with techniques for the functional simulation of very large digital systems. We consider techniques that are a hybrid of classical compiled code simulation and recent branching program based simulation in order to resolve memory performance problems inherent to BDD based cycle simulation. Specifically, predefined functional units (“macros”) are extracted from the circuit and evaluated directly instead of building BDDs for them. The functionality of those macros, such as multipliers, filters, etc., can in turn be verified by simulation of their gate-level implementations respectively or by formal verification techniques. Our results demonstrate that this approach leads to considerably faster simulation.