Input-queued cell switches employing the oldest-cell-first (OCF) policy have been shown to yield low mean delay characteristics. Moreover, it has been proven that OCF is stable for admissible traffic conditions when executed with a scheduling speedup of 2. However, as link speeds increase, the computational complexity of these algorithms limits their applicability in high port-density switches and routers. To address the scalability issue, we describe a Frame-Based Maximal Weight Matching (FMWM) algorithm, employing OCF as queue weights, in which a new scheduling decision is issued once every several cell times. Between scheduling decisions, the configuration of the crossbar switch remains unchanged. We further extend the analysis to address the case of multiple classes of service, and prove that the algorithm is stable with an internal buffer transfer speedup of 2, thereby significantly relaxing the timing constraints imposed on the scheduling process.

There have been countless efforts directed toward efficiently controlling the flow of vehicular traffic through an intersection. This paper describes an algorithm designed for the signal control problem that employs concepts drawn from the field of packet switching in computer networks. The novel method proposed utilizes a maximal weight matching algorithm to minimize the queue sizes at each approach, yielding significantly lower average vehicle delay through the intersection. Of particular interest are scenarios in which differentiated services are offered to vehicle classes with differing priorities. Lyapunov function-based analysis is provided, deriving the conditions under which the system is guaranteed to be stable. The algorithm is compared to an optimized fixed-time controller and a vehicle-actuated controller using the VISSIM traffic simulation environment. Simulation results demonstrate the performance gain obtained when using the proposed scheme, particularly in the scenario in which vehicle routes are unequally distributed, and multiple classes of service are desired.

This brief presents an efficient and scalable online learning algorithm for recurrent neural networks (RNNs). The approach is based on the real-time recurrent learning (RTRL) algorithm, whereby the sensitivity set of each neuron is reduced to weights associated with either its input or output links. This yields a reduced storage and computational complexity of O(N(2)). Stochastic meta descent (SMD), an adaptive step size scheme for stochastic gradient-descent problems, is employed as means of incorporating curvature information in order to substantially accelerate the learning process. We also introduce a clustered version of our algorithm to further improve its scalability attributes. Despite the dramatic reduction in resource requirements, it is shown through simulation results that the approach outperforms regular RTRL by almost an order of magnitude. Moreover, the scheme lends itself to parallel hardware realization by virtue of the localized property that is inherent to the learning framework.

This paper introduces a novel architecture for performing the core computations required by dynamic programming (DP) techniques. The latter pertain to a vast range of applications that necessitate an optimal sequence of decisions to be issued. An underlying assumption is that a complete model of the environment is provided, whereby the dynamics are governed by a Markov decision process (MDP). Existing DP implementations have traditionally been realized in software. Here, we present a method for exploiting the data parallelism associated with computing both the value function and optimal action set. An optimal policy is obtained four orders of magnitude faster than traditional software-based schemes, establishing the viability of the approach for real-time applications

To resolve the high memory bandwidth requirements presented by output-queued switches, several parallel shared-memory architectures have been previously proposed. In this paper, our goal is to extend existing shared-memory architecture results while introducing the notion of Fabric on a Chip (FoC). In taking advantage of recent advancements in integrated circuit technologies, FoC aims to facilitate the consolidation of as many packet switching functions as possible on a single chip. Accordingly, this paper focuses a novel pipelined memory management algorithm which plays a key role in the context of on-chip output-queued switch emulation. We discuss in detail the fundamental properties of the proposed scheme, along with FPGA-based implementation results that illustrate its scalability and performance attributes.

The distributed shared memory (DSM) packet switching architecture has attracted much attention recently, predominantly due to its ability to overcome the inherent memory-bandwidth limitation of output-queued switches. Its performance has been studied from a theoretical point of view by exploring the conditions under which it can emulate an output-queued switch. At the core of the DSM design is a memory management algorithm that determines the memory units to which arriving packets are forwarded. However, the complexity of such algorithms found to date is O(N), where N denotes the number of ports in the system, thereby inherently limiting the scalability of the scheme. In this paper, we propose a novel pipelined memory management algorithm for DSM switches which offers reduced timing complexity at the cost of fixed latency. Moreover, we demonstrate how processing and memory-access speedup factors yield a highly scalable DSM switch architecture design.

We present an innovative MAC protocol (Q-MAC) that minimizes the energy consumption in multi-hop wireless sensor networks (WSNs) and provides quality of service (QoS) by differentiating network services based on priority levels. The priority levels reflect application priority and the state of system resources, namely residual energy and queue occupancies. The Q-MAC utilizes both intra-node and inter-node arbitration. The intra-node packet scheduling is a multiple queuing architecture with packet classification and weighted arbitration. We also introduce the power conservation MACAW (PC-MACAW) - a power-aware scheduling mechanism that, together with the loosely prioritized random access (LPRA) algorithm, govern the inter-node scheduling. Performance evaluation are conducted between Q-MAC and S-MAC with respect to two performance metrics: energy consumption and average latency. Simulation results indicate that the performance of the Q-MAC is comparable to that of the S-MAC in non-prioritized traffic scenarios; when packets with different priorities are present, Q-MAC supiors in average latency differentiation between the classes of service, while maintaining the same energy level as that of S-MAC

Determining queue urgency (or weight) is a fundamental challenge, particularly in the context of high-speed packet switching. Weighting schemes have significant impact on the decisions made by arbitration and/or scheduling mechanism, thus directly shaping the overall performance of the system. Various weight functions, including iterative longest-queue-first (iLQF) and iterative oldest-cell-first (iOCF) have been presented in the literature. However, existing schemes suffer from limited performance in the presence of non-ideal traffic patterns. In this paper, we introduce the cumulative waiting-time (CWT) queue-weighting scheme, which is a pragmatic mechanism for dynamically determining the queue weight based on its aggregated cells waiting time.

The paper presents an analysis of output queued cell switches which are introduced with generic non-uniformly distributed traffic. Random arbitration is employed whereby non-empty queues compete equally for service within each switching interval. In particular, we study the case of two-state Markov-modulated arrivals in which input ports generate bursty streams that are non-uniformly distributed. Under the assumption of a memoryless server, the probability generating function of the interarrival process is utilized to derive closed-form expressions for the queue size distribution. The methodology established forms a flexible tool in determining bounds on the behavior and expected performance of output queued switches under a range of traffic scenarios. The validity of the analytical inference is established through simulation results.

Virtual queueing is commonly deployed as a buffering technique in high-performance input-queued switch architectures. This paper presents the analysis for discrete-time virtual output queued switches with incoming traffic governed by a uniformly distributed Markov modulated on/off process, and geometrically distributed service times. We utilize the k-step first-passage time probability matrix to derive the probability generating function of the inter-arrival times distribution. Based on the latter, closed-form expressions for the queue size distribution and mean delay are obtained. The validity of the analysis is established through computer simulations.

In this paper a high-performance, robust and scalable scheduling algorithm for input-queued switches, called distributed sequential allocation (DISA), is presented and analyzed. Contrary to pointer-based arbitration schemes, the algorithm proposed is based on a synchronized channel reservation cycle whereby each input selects a designated output, considering both its local requests as well as global channel availability information. The distinctiveness of the algorithm is in its ability to offer high-performance when multiple cells are transmitted within each switching intervals. The subsequent relaxed switching-time requirement allows for the utilization of commercially available crosspoint switches, yielding a pragmatic and scalable solution for high port-density switching platforms. The efficiency of the algorithms and its robustness is established through analysis and computer simulations addressing diverse traffic scenarios.

This paper presents and analyzes a high-performance, robust, and scalable scheduling algorithm for input-queued switches called distributed sequential allocation (DISA). In contrast to pointer-based arbitration schemes, the proposed algorithm is based on a synchronized output reservation process, whereby each input selects a designated output while taking into consideration both local transmission requests and the availability of global resources. The distinctiveness of the algorithm lies in its ability to offer high performance when multiple cells are transmitted within each switching interval. Relaxed switching-time requirements allow for the incorporation of commercially available crosspoint switches. The result is a pragmatic and scalable solution for high port-density switching platforms. The efficiency of the scheme and its robustness in the presence of admissible traffic, without the need for speedup, is established through analysis and computer simulations. Performance results are shown for various traffic scenarios including nonuniform destination distribution, correlated arrivals and multiple classes of service.

The provision of quality-of-service (QoS) is a predominant requirement from modern high-performance switches and routers. Port densities of tens and even hundreds of ports characterize ATM and IPv6 switches where each port carries high-speed traffic with diverse statistical characteristics. In this paper a scheduling scheme for Tbit/sec, input-queued, WDM packet-switch networks is presented. The proposed architecture is contention-free, scalable, easy to implement and requires no internal "speedup". Moreover, the scheme inherently supports per-class QoS. Non-uniform destination distribution and bursty cell arrivals are studied for a switch with an aggregated capacity of 1 Tbit/sec. Simulation results show that class-differentiated low latency is achieved, yielding a powerful solution for high-performance packet-switch networks.

A novel binary number system, called Redundant Linear Coding (RLC), is presented. By eliminating the need for carry handling, a feasible tradeoff between speed and area yields short computation time for up/down counting and comparison operations. The scheme can efficiently be applied to a wide range of high-speed digital applications.

A novel approach to accurate and robust image registration using feedforward neural networks is presented. Common registration schemes utilize some form of similarity measures in order to evaluate affine transformation parameters. In the proposed scheme, feedforward neural networks are employed as a means of providing translation, rotation and scaling parameters with respect to reference and observed image sets. Discrete cosine transform (DCT) features are extracted as inputs to the network. Experimental results with several deformed and noisy images indicate that the proposed algorithm is both accurate and remarkably robust to diverse noisy conditions.