Demo Data from VLDB 2026 / reviewers in the wild / expert
Yueh-Hsung Su
dblp:93/4958
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 1970
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorTheory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 74% Integrated circuit design · 26% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 2 | 1969 | Computer Reduction of Two-Level, Multiple-Output Switching Circuits · IEEE Trans. Computers 1969 Logic Design Automation of Fan-In Limited NAND Networks · IEEE Trans. Computers 1969 |
Integrated circuit design › asynchronous circuit design
asynchronous sequential machine |
0.0 | 1 | 1969 | Shift Register Realizations of Asynchronous Sequential Machines · Inf. Control. 1969 |
Electronic design automation › logic synthesis › logic minimization
multiple output minimization |
0.0 | 1 | 1969 | Computer Reduction of Two-Level, Multiple-Output Switching Circuits · IEEE Trans. Computers 1969 |
Electronic design automation › logic synthesis › sequential circuit synthesis
shift-register realization |
0.0 | 1 | 1969 | Shift Register Realizations of Asynchronous Sequential Machines · Inf. Control. 1969 |
Electronic design automation › logic synthesis
two-level logic minimization |
0.0 | 1 | 1969 | Computer Reduction of Two-Level, Multiple-Output Switching Circuits · IEEE Trans. Computers 1969 |
Integrated circuit design › digital circuit design
combinational logic |
0.0 | 1 | 1969 | Computer Reduction of Two-Level, Multiple-Output Switching Circuits · IEEE Trans. Computers 1969 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1969 | Computer Reduction of Two-Level, Multiple-Output Switching Circuits · IEEE Trans. Computers 1969 |
Electronic design automation › logic synthesis › circuit optimization
gate-count minimization |
0.0 | 1 | 1969 | Logic Design Automation of Fan-In Limited NAND Networks · IEEE Trans. Computers 1969 |
Integrated circuit design › digital circuit design
sequential circuit design |
0.0 | 1 | 1969 | Shift Register Realizations of Asynchronous Sequential Machines · Inf. Control. 1969 |
Methods — techniques the papers use, named apart from their topics
heuristic minimization · 0.0factoring · 0.0FORTRAN program · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1970 | R70-30 Fuzzy Logic and Its Application to Switching SystemsabstractOne of the problems in computer science is the gap between natural languages for human beings and programming languages for digital computers, since the former are much more complex than the latter. This is due to the fact that natural languages are fuzzy in nature but programming languages are precise. For example, when we say that a certain university is a good university, fuzziness arises since there is no sharp boundary between a good university and an average one. A university may be good from one person's point of view, but may be considered as just an average one in another person's opinion. To solve a problem by a computer, a great deal of time and energy would be saved if the computer could understand either natural languages themselves or something close to them. In other words, computers would become more powerful if they could accept fuzzy concepts similar to the capability of a human brain. Yueh-Hsung Su |
IEEE Trans. Computers | 1 |
| 1969 | Shift Register Realizations of Asynchronous Sequential Machines
Yueh-Hsung Su |
Inf. Control. | 1 |
| 1969 | Logic Design Automation of Fan-In Limited NAND NetworksabstractFactoring techniques are incorporated in computer-oriented algorithms for the synthesis of fan-in limited NAND switching networks. Tree networks with reduced gate count or levels of logic are sought. While example FORTRAN programs emphasize computer execution of the algorithms, they are also efficient for hand execution. Donald L. Dietmeyer, Yueh-Hsung Su |
IEEE Trans. Computers | 2 |
| 1969 | Computer Reduction of Two-Level, Multiple-Output Switching CircuitsabstractAn algorithm which reduces the number of gates and connections (diodes) in two-level, multiple-output combinational logic networks is presented and compared with conventional minimization procedures. Yueh-Hsung Su, Donald L. Dietmeyer |
IEEE Trans. Computers | 1 |