In WSN (Wireless Sensor Network), the sensor nodes may become faulty due to low battery power or some other physical defects. The faulty nodes may badly affect the network performance while trying to reach an agreement on an event. This effectively leads to deviation from the desired outcome, ineffective utilization of network bandwidth and unproductive computational overhead. In this work, we propose a CA (Cellular Automata) based scheme that can efficiently identify the faulty nodes of a WSN in operation. The scheme is developed around the SACA (Single Attractor CA) to enable diagnosis of the network region with affected nodes, without consuming massive computational overhead and bandwidth.

The wireless sensor network (WSN) encounters resource restrictions such as low computational power, reduced bandwidth & limited power resource and it demands efficient management of such resources. This work proposes a scheme (SSMCA), developed around the cellular automata (CA), for efficient management of battery power in sensor nodes with optimized cost of implementation. Each sensor node is assumed to be equipped with a segment of the CA, selected for the network that defines the state (active/standby) of the node at next time instant. The CA based management of status (active/standby) of a node ensures the reduced battery power consumption in nodes of a cluster as well as in the whole sensor network. As a segment of the CA is planted within a node, the additional cost for implementation of the proposed scheme is marginal. The simulation results establish that the SSMCA can better utilize the resources and ensure a maximally covered energy efficient sensor network.

This paper reports an efficient synthesis scheme for pseudorandom pattern generators (PRPGs) of arbitrary length. The$n$-bit PRPG, synthesized in linear time$(O(n))$, generates quality pseudorandom patterns leading to a highly efficient test logic for the very-large-scale integration (VLSI) circuit. The cascadable structure of proposed$n$-cell PRPG is utilized to construct the$(n+1)$-cell PRPG, in two time steps, without sacrificing the pseudorandomness quality. This eases the design of on-chip test pattern generators for the system-on-a-chip implementing multiple cores. It avoids the requirement of disparate test hardware for different cores and thereby ensures drastic reduction in the cost of test logic. The effective characterization of nonlinear cellular automata (CA) provides the foundation of such a design. Extensive experimentation confirms the better efficiency of the proposed test structure compared to that of the conventional designs, developed around maximal length CA/linear feedback shift register of$O(n^{3})$complexity.

This paper reports synthesis of a built-in self-test logic for the cores integrated into an SoC. The test logic is developed around a nonlinear cellular automata (CA). The CA based scalable PRPG, synthesized in linear time (O(n)), enables the design of such a highly efficient test logic. The cascadable structure of the PRPG is utilized to construct the on-chip Test Pattern Generators (TPGs) for the SoC implementing multiple cores. It avoids the requirement of disparate test hardware for the SoC cores and thereby ensures drastic reduction in the cost of test logic. Extensive experimentation confirms the better efficiency of the proposed test structure than that of the conventional designs, developed around maximal length CA/LFSR.

This work targets modeling traffic flow in roads of a congested city. The cellular automata (CA) have been configured for such modeling. The urban traffic models, in general, concentrate on low traffic density. The inabilities of traditional models to address the issues arise out of heavy traffic in crowded cities of third world countries are properly addressed in the proposed elementary CA based model. The effectiveness of the model is verified considering the traffic in Kolkata. It is established that the model can fairly reproduce various traffic conditions as found empirically. Further, the proposed model succeeds the limitations of traffic flow models in congestion and also reproduces the empirical results.

Sensor network has been identified as the most important technology for the next century. Despite of its potential application, wireless sensor network encounters resource restrictions such as low computational power, reduced bandwidth and specially limited power resource. This work reports a network monitoring protocol to provide a logical topology for an energy efficient maximally covered ad-hoc sensor network (Eemca). It is developed around the regular structure of 1-dimensional cellular automata. The simulation results establish that the monitoring of sensor nodes with the proposed technique shows better utilization of the resources that effectively leads to an energy efficient maximally covered sensor network topology.

This paper reports a scheme for cost optimal design of PRPG, built around nonlinear cellular automata (CM). The characterization of 3-neighborhood CA rules provides the foundation of designing the n-bit PRPG in linear time. The GA (genetic algorithm) framework proposed to evolve the CA results in a minimal cost PRPG structure, in terms of area overhead and delay

This work presents an efficient scheme for processing queries on location dependent data in a cellular mobile environment. It is developed around the theory of cellular automata (CA) which act as a search engine and implements computation for query processing that either can be done at the network base station or at the mobile unit depending on the requirement specified by the service provider. The scheme also ensures efficient handling of disconnection problem due to hand-off. The experimental results confirm that the overhead & delay, query processing, in the proposed scheme is much less than that of the existing schemes.

This paper reports the design of an efficient test set generator (TSG) for VLSI circuit. It is built around the regular structure of cellular automata (CA) employing nonlinear CA rules and targets detection of hard-to-detect pseudo-random pattern resistant faults. The optimal design of TSG structure is achieved with the framework of SA (simulated annealing) to ensure proper selection of CA rules for TSG cells. Efficiency of TSG in comparison to linear CA/LFSR based designs is validated through experimentation.

This paper reports an efficient design of test pattern generators (TPGs) for a chip having multiple cores. It is built around nonlinear cellular automata (CA) based pseudo-random pattern generator (PRPG). The modular and cascadable structure of proposed n-cell PRPG can be utilized to construct the (n+1)-cell PRPG without sacrificing the pseudo-randomness quality. The efficiency of such a scalable PRPG structure is demonstrated in designing the on-chip TPGs for a VLSI chip implementing multiple cores.

This paper reports an efficient BIST solution for VLSI circuits. The solution is based on an onchip Pseudo-Random Pattern Generator (PRPG). The test solution guarantees non-issuence of the test patterns declared prohibited to a CUT (Circuit Under Test). It has been developed around non-linear Cellular Automata (CA) and provides a linear time solution of designing an n-bit PRPG. Experimental results confirm the enhanced pseudo-random quality of the test patterns due to application of non-linear CA rules.

This paper reports the design of an on-chip Test Pattern Generator (TPG) for VLSI circuits that avoids generation of a given Prohibited Pattern Set (PPS). The design ensures desired pseudo-random quality of the test patterns generated while ensuring fault coverage close to the figures achieved with a typical Pseudo Random Pattern Generator (PRPG) designed around maximal length LFSR/CA. The theoretical framework of CA has provided the foundation of this work. A GA based evolution scheme is employed to achieve the desired TPG developed over the theory of cellular automata.