While optimizing for core hardware performancerelated target metrics, frameworks for approximate accelerators often overlook the reliability aspect. Approximated implementations obtained by these frameworks can potentially differ in terms of reliability and may impact the reliability of the overall system. In particular, approximation changes the data profiles transmitted between system modules, which can trigger crosstalk on interconnect lines and aggravate electromigration. We propose a two-stage process that performs a reliability assessment of the circuit interconnects after the approximate accelerator synthesis. Our approach aims to find the most reliable solutions from the approximate candidate circuits generated by an automated approximation flow. We then leverage Pareto-filtering to strike a balance between area, reliability, and accuracy. Notably, the selected designs achieve up to a 178% improvement in mission time compared to the original accelerator, and a 68% improvement over designs optimized solely for area. In addition, our methodology allows custom priority settings to be adaptable to a user's preference, thereby leading to circuits that meet diverse design constraints. Our experimental results show the effectiveness of our methodology in achieving superior trade-offs between area, reliability, and accuracy, hence uncovering a new dimension for approximate accelerator design methodologies.

Abstract Safety-critical automotive systems require on-chip testing methods to ensure high fault coverage and reliable operation. Periodic Deterministic Logic Built-In Self-Test (DLBIST) is often used to meet these demands. For automotive applications, DLBIST must operate reliably despite temperature variations, including those caused by ambient changes and self-heating in FinFET transistors. A test set effective for all temperatures typically requires a large volume, which can make DLBIST impractical. This paper proposes a robust DLBIST scheme which applies multiple voltages during power-on and power-off tests and the optimal or adapted voltage during periodic tests in system operation. If distributed sensors for on-chip temperature are available for DVFS control, they can be exploited for an adaptive DLBIST scheme. During the periodic test phase, the BIST Control Unit (BCU) dynamically selects and applies the pre-generated test set corresponding to the current operating voltage and measured temperature. This adaptive selection ensures that testing conditions precisely match the real operating points. If temperature sensors are not available, testing at the so-called Zero Temperature Coefficient (ZTC) voltage is one alternative, which is the voltage where the temperature-induced variability is minimized. This makes periodic DLBIST a feasible solution for in-field self-testing, even in cases where on-chip temperature sensors are not available.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

Abstract It has been known and explored for many years that low voltage testing amplifies the effect of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning SDFs into easily detectable stuck-at-faults. It is often overlooked that $$V_{\textrm{min}}$$ V min testing poses an additional challenge to the test pattern generation method under process variations. The standard deviation of gate delays under $$V_{\textrm{min}}$$ V min is a multiple of that under nominal voltage. The increased variation will invalidate the efficiency of test patterns generated under nominal voltage and significantly reduce fault coverage. This paper presents the first algorithm for test pattern generation specifically tuned for $$V_{\textrm{min}}$$ V min testing which obtains higher fault coverage by smaller test sets than those generated for nominal voltage. The patterns applicable to other voltage levels can be derived from the pattern set generated under extreme variations at low supply voltage. Experimental results demonstrate that the proposed method produces test patterns that outperform N-detection test sets in terms of test set volume and fault efficiency across different voltage levels.

Logic Built-In Self-Test (LBIST) with stored deterministic patterns is supported by the major CAD vendors and is gaining increasing attention, especially for safety-critical applications such as automotive. It is used for both manufacturing and periodic in-field testing. An unresolved challenge so far stems from the inevitable process variations. This paper presents the first approach for storage-based BIST addressing delay faults under process variations and multiple voltages. A unified solution for pattern generation, test set compaction and BIST hardware is presented that is compatible with commercial schemes. The solution significantly outperforms traditional N-detect for transition faults in terms of test set size, test application time and fault efficiency.

Process, Voltage, Temperature (PVT) variations impede the test generation for Small Delay Faults (SDFs) significantly as test patterns effective for one circuit instance may not be valid for a different one. Temperature-induced timing variations in FinFET and Gate-All-Around (GAA) technologies are especially severe due to temperature fluctuations and self-heating. Depending on the supply voltage, they show the Temperature Effect Inversion (TEI) which describes the increase of the circuit speed with increasing temperature. The Zero Temperature Coefficient (ZTC) specifies a supply voltage where TEI approaches 0, and the optimal voltage is determined, such that the effects of temperature-induced variability are minimized. Simulation results are reported, which demonstrate that test generation at the ZTC voltage leads to higher fault coverage of SDFs while using significantly less test patterns.

Many applications allow errors during communication as long as their sizes or rates are limited. These applications are perfect candidates for approximate communication and provide sufficient degrees of freedom to optimize the communicated data for performance, power, reliability and safety within certain error bounds. In this study, we present a novel approach for approximate communication which is specifically tailored to the streaming of data between sensors and control units on narrow parallel buses. To meet the performance goals, the presented approach relies on base-delta compression, where a base value is followed by a sequence of differences to it (deltas). To ensure an efficient low power transmission of data as well as a high reliability and safety at the same time, the approach uses a Gray code for bus encoding and approximates the data within given error bounds, such that crosstalk induced faults and currents are minimized and the overall switching activity is kept low.

Interconnect is essential for the performance, power consumption, and safety of modern digital circuits. In the context of approximate computing, various methods have been proposed to improve the system performance by decreasing the amount of transmitted data or reducing power consumption through reduced switching activity on the interconnects. However, their impact on the reliability and safety of interconnect has not yet been evaluated. In this work, the effects of approximate communication on the reliability and safety of interconnects in digital circuits are assessed. The results show that while these methods increase performance, they can also harm the reliability and mission time of interconnects. We propose some modifications to address the safety and reliability issues when using approximate communication. Our results show that these modifications can increase the mission time, and establish a proper balance between performance, power consumption, and safety.

Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation. Since process variations can invalidate the effectiveness of such patterns, different circuit instances may show a different fault coverage for the same test pattern set. This paper presents a method to generate test pattern sets for SDFs which are valid for all circuit timings. The method overcomes the limitations of known timing-aware Automatic Test Pattern Generation (ATPG) which has to use fault sampling under process variations due to the computational complexity. A statistical learning scheme maximises the coverage of SDFs in circuits following the variation parameters of a calibrated industrial FinFET transistor model. The method combines efficient ATPG for Transition Faults (TFs) with fast timing-aware fault simulation on GPUs. Simulation experiments show that the size of the pattern set is significantly reduced in comparison to standard N-detection while the fault coverage even increases.

Abstract Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.

Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time. To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST. Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.

In today’s system-on-chips, interconnect has an important role and affects the system’s reliability more than in conventional technologies. Interconnects suffer from crosstalk defects that result in delay and glitch faults. Furthermore, fab-induced variations lead to different sizes of crosstalk defects. The largest crosstalk defects are detected by conventional interconnect test methods, while the smaller ones do not change the system behavior and are left without detection. In this paper, we show that even smaller crosstalk defects have an inevitable impact on electro-migration (EM) degradation. They increase the current that conveys through the wire and consequently result in more EM degradation and shorter mean time to failure of the system. Simulation results show that in the worst case the EM degradation increases up to 90%, however, even in the normal situation 7.2% degradation can be observed for the PARSEC 2000 benchmark Because these Hidden Interconnect Defects cause different small delay sizes, we propose a multi-frequency test method to detect them properly. Our experimental results for 8000 different 32-bit interconnect layouts show that, on average, 6 frequencies and 81 test patterns are required for finding hidden interconnect defects.

The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with several different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors.

Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years, small delay faults (SDFs) have gained increasing attention as possible indicators of marginal hardware. However, SDFs on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults (HDFs), but so far FAST has mainly been restricted to manufacturing test. This paper presents a fully autonomous built-in self-test approach for FAST, which supports in-field testing by appropriate strategies for test generation and response compaction. In particular, the required test frequencies for HDF detection are selected, such that hardware overhead and test time are minimized. Furthermore, test response compaction handles the large number of unknowns (X-values) on long paths by storing intermediate MISR-signatures in a small on-chip memory for later analysis using X-canceling transformations. A comprehensive experimental study demonstrates the effectiveness of the presented approach. In particular, the impact of the considered fault size is studied in detail.

Aging monitors can indicate the wear-out phase of a semi-conductor device before it will actually fail, and allow the use of integrated circuits in applications with high safety and reliability demands. In the early phase of the lifecycle of integrated systems, small delay faults may indicate reliability problems and early life failures, even if they are smaller than the slack of any path and neither alter the functional behavior of a system nor violate any aging guardband. One option to detect this type of hidden delay faults (HDFs) is the application of a faster-than-at-speed-test (FAST). This paper shows that aging monitors can be extended at low cost to achieve high HDF test coverage with a reduction in test time during FAST. The result is a unified strategy to improve the reliability in both early and late phases of the system lifecycle.

Small delay faults on short paths may be undetectable even during at-speed test. Faster-than-at-speed test (FAST) targets these hidden delay faults by overclocking the circuit, typically using several different test frequencies. Due to the shorter clock periods, the output values on long paths may not stabilize fast enough, and the resulting unknown values (X-values) aggravate test response compaction. As the number and the distribution of X-values vary with the test frequency, X-handling for FAST must be very flexible. Most of the state-of-the-art approaches for X-tolerant test response compaction are not designed for varying X-profiles. Yet, the stochastic compactor by Mitra et al. offers an easily programmable solution, as the com¬paction logic is controlled by weighted pseudo-random signals. An optimal setup, however, cannot be guaranteed in a FAST scenario. To better adapt the scheme to FAST, the compactor is partitioned into several smaller compactors and the scan outputs are properly assigned to compactor inputs. Finding the best setup then corresponds to a clustering problem, for which several algorithms are presented. Experimental results show that the number of X-values at the compactor outputs can be significantly reduced while maintaining the fault efficiency.

Small Delay Faults (SDFs) on short paths may escape even state-of-the-art at-speed tests. Faster-than-at-Speed Test (FAST) works with increased clock frequencies to detect these faults. However, FAST also introduces an increased amount of unknown logic values (X-values) into the test responses, which makes test response compaction difficult. The paper at hand presents and evaluates a Design for Test (DFT) approach specifically tuned to FAST. It utilizes a special scan-chain configuration in combination with an adaptive masking scheme - the required mask data is generated by respective frequency-aware algorithms. Experimental results indicate that this combination of scan-chain configuration and output masking can achieve high reduction in X-values (up to 95%) without too much loss of fault information at a reasonable amount of control overhead. The approach also has a significant impact on the number of intermediate signatures required by an X-canceling MISR, which can be reduced by up to 68%.

On behalf of the Program, Organizing, and Steering Committees, we would like to extend a warm welcome to everyone attending the European Test Symposium 2017 (ETS'17). ETS has been established as one of the main international forums and the larger forum in Europe that brings together the test community to discuss emerging ideas, views, and trends in the area of electronic-based circuits and system testing. Topics of interest include, but are not limited to, design-for-test, dependability, security, failure analysis and diagnosis, on-line test, automated test hardware, validation and verification, fault simulation, fault tolerance, automatic test generation, etc.

In recent years early life failures have caused several product recalls in semiconductor and automotive industries associated with a loss of billions of dollars. They can be traced back to various root-causes. In embedded or cyber-physical systems, the interaction with the environment and the behavior of the hardware/software interface are hard to predict, which may lead to unforeseen failures. In addition to that, defects that have escaped manufacturing test or “weak” devices that cannot stand operational stress may for example cause unexpected hardware problems in the early life of a system. The special session focuses on the first aspect. The first contribution discusses how the interaction with the environment in cyber-physical systems can be appropriately modeled and tested. The second presentation then deals with a cross-layer approach identifying problems at the hardware/software interface which cannot be compensated by the application and must therefore be targeted by specific tests.

Faster-than-at-Speed Test (FAST) can be used to detect Hidden Small Delay Faults (HDFs), which are escaping a conventional at-speed test. However, due to the overclocking of the Circuit Under Test (CUT), a high number of X-values are introduced into the test responses, since the corresponding outputs have not yet stabilized at the target observation time. Furthermore, the X-ratio varies significantly with the observation time, consequently posing a great challenge to compactor designs. In this paper, a novel Scan-Flip-Flop (SFF) clustering method is presented to generate scan-chains which support an efficient response compaction for FAST. Clustering is done both by analyzing the circuit's topology and by timing-accurate simulation of a test set. An efficient graph-based algorithm clusters the SFFs, such that the X-values are accumulated in only few scan-chains.Experimental results verify that blocking the chains with highest X-density can significantly decrease the X-ratios of the remaining chains while maintaining a high fault efficiency. Compared to a random configuration the observed improvement can be up to 4 times higher.Since no actual ordering is imposed on the SFFs inside a scan-chain, the proposed algorithm still leaves a high degree of freedom for further scan-chain optimization with respect to different cost metrics.

Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden delay faults (HDFs) do not influence the circuit's behavior initially, but they may indicate design marginalities leading to early-life failures, and therefore they cannot be neglected. HDFs can be detected by faster-than-at-speed test (FAST), where typically several different frequencies are used to maximize the coverage. A given set of test patterns P potentially detects a HDF if it contains a test pattern sensitizing a path through the fault site, and the efficiency of FAST can be measured as the ratio of actually detected HDFs to potentially detected HDFs. The paper at hand targets maximum test efficiency with a minimum number of frequencies. The procedure starts with a test set for transition delay faults and a set of preselected equidistant frequencies. Timing-accurate simulation of this initial setup identifies the hard-to-detect faults, which are then targeted by a more complex timing-aware ATPG procedure. For the yet undetected HDFs, a minimum number of frequencies are determined using an efficient hypergraph algorithm. Experimental results show that with this approach, the number of test frequencies required for maximum test efficiency can be reduced considerably. Furthermore, test set inflation is limited as timing-aware ATPG is only used for a small subset of HDFs.

Small delay faults may be an indicator of a reliability threat, even if they do not affect the system functionality yet. In recent years, Faster-than-at-Speed-Test (FAST) has become a feasible method to detect faults, which are hidden by the timing slack or by long critical paths in the combinational logic. FAST poses severe challenges to the automatic test equipment with respect to timing, performance, and resolution. In this paper, it is shown how logic built-in self-test (BIST) or embedded deterministic test can be used for an efficient FAST application. Running BIST just at a higher frequency is not an option, as outputs of long paths will receive undefined values due to set time violations and destroy the content of the signature registers. Instead, for a given test pattern sequence, faults are classified according to the optimal detection frequency. For each class, a MISR-based compaction scheme is adapted, such that the critical bits to be observed can be determined by algebraic computations. Experiments show that rather a small number of inter-mediate signatures have to be evaluated to observe a large fraction of hidden delay faults testable by the given test sequence.

Efficient diagnosis procedures are crucial both for volume and for in-field diagnosis. In either case the underlying test strategy should provide a high coverage of realistic fault mechanisms and support a low-cost implementation. Built-in self-diagnosis (BISD) is a promising solution, if the diagnosis procedure is fully in line with the test flow. However, most known BISD schemes require multiple test runs or modifications of the standard scan-based test infrastructure. Some recent schemes circumvent these problems, but they focus on deterministic patterns to limit the storage requirements for diagnostic data. Thus, they cannot exploit the benefits of a mixed-mode test such as high coverage of non-target faults and reduced test data storage. This paper proposes a BISD scheme using mixed-mode patterns and partitioning the test sequence into “weak” and “strong” diagnostic windows, which are treated differently during diagnosis. As the experimental results show, this improves the coverage of non-target faults and enhances the diagnostic resolution compared to state-of-the-art approaches. At the same time the overall storage overhead for input and response data is considerably reduced.

Robust circuits are able to tolerate certain faults, but also pose additional challenges for test and diagnosis. To improve yield, the test must distinguish between critical faults and such faults, that could be compensated during system operation, in addition, efficient diagnosis procedures are needed to support yield ramp-up in the case of critical faults. Previous work on circuits with time redundancy has shown that "signature rollback" can distinguish critical permanent faults from uncritical transient faults. The test is partitioned into shorter sessions, and a rollback is triggered immediately after a faulty session. If the repeated session shows the correct result, then a transient fault is assumed. The reference values for the sessions are represented in a very compact format. Storing only a few bits characterizing the MISR state over time can provide the same quality as storing the complete signature. In this work the signature rollback scheme is extended to an integrated test and diagnosis procedure. It is shown that a single test run with highly compacted reference data is sufficient to reach a comparable diagnostic resolution to that of a diagnostic session without any data compaction.

Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality.

To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simu-lations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defect-induced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45nm technology.

Nano-electronic circuits and systems are affected by increasing parameter variations and by an increasing susceptibility to soft errors. To improve yield and to compensate errors online, fault tolerance must be added to the design. Observing only the input/output behavior during manufacturing test would be too optimistic for such robust designs, whereas a purely structural test relying on DFT can be disturbed by soft errors and lead to an unnecessary yield loss. As a solution for circuits with time redundancy, “signature rollback” has been proposed, which partitions the test into shorter sessions and triggers a rollback after a faulty session to distinguish permanent from transient faults. It has been shown that both the test time and the yield loss decrease with the number of test sessions, but the hardware overhead increases. This paper proposes a solution with reduced hardware overhead by combining signature rollback with extreme space compaction. The new scheme is validated both analytically and by simulation experiments.

Previous work on testing NoC-based systems has shown that the integrated network can be efficiently reused as test access mechanism (TAM). These approaches exploit the given infrastructure for data transportation. Beyond that, NoC-architectures for nanoscale systems also have to ensure a reliable communication by additional hardware and/or software measures. For example a cyclic redundancy check (CRC) may be added to protect the end-to-end communication between network resources. This paper presents an approach to reuse the CRC hardware for a compression scheme similar to LFSR-reseeding. The experimental results show that competitive compression ratios can be achieved at low extra cost. This way, core testing in NoC-based systems can benefit from test data compression even for standard cores without integrated decompressors.

Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considered, but also its robustness properties have to be analyzed. In this work we propose a method to verify the strong fault-secureness by use of constrained SAT-based ATPG. Strongly fault-secure circuits can be seen as the widest class of circuits achieving the totally self-checking (TSC) goal, which requires that every fault be detected the first time it manifests itself as an error at the outputs. As the strongly fault-secure property guarantees to achieve the TSC goal even in the case of fault accumulation, the effects of all possible fault sequences have to be taken into consideration to verify this property. To speed up the complex analysis of multiple faults we develop rules to derive detectability or redundancy information for multiple faults from the respective information for single faults. For the case of not strongly fault-secure circuits our method provides measures to grade the ldquoextentrdquo of strong fault-secureness given by the implementation.

Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect and compensate errors online. However, during synthesis and optimization self-checking properties can be destroyed. This paper shows how automatic test pattern generation (ATPG) can be used to analyze self-checking properties. As a result the properties are either verified or the fault detection profile provided by ATPG can be used to increase the error detection or fault tolerance capabilities of the design. Experimental data are shown for several self-checking arithmetic circuits.

An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Most of the existing built-in self-repair solutions reuse IP-Cores for BIST without modifications. However, this prevents an optimized test and repair interaction. In this paper, the concept of modular BIST for memories is introduced, which supports a more efficient interleaving of test and repair and can be achieved with only small modifications in the BIST control.

Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a robust design has become mandatory. However, standard structural test procedures still address classical fault models and cannot deal with the non-deterministic behavior caused by parameter variations and other reasons. Chips may be rejected, even if the test reveals only non-critical failures that could be compensated during system operation. This paper introduces a scheme for embedded test, which can distinguish critical permanent and non-critical transient failures for circuits with time redundancy. To minimize both yield loss and the overall test time, the scheme relies on partitioning the test into shorter sessions. If a faulty signature is observed at the end of a session, a rollback is triggered, and this particular session is repeated. An analytical model for the expected overall test time provides guidelines to determine the optimal parameters of the scheme.

An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare rows and columns (2D redundancy). To avoid the storage of large failure bitmaps needed by classical algorithms for offline repair analysis, existing heuristics for built-in repair analysis (BIRA) either follow very simple search strategies or restrict the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to high test times. The integrated built-in test and repair approach proposed in this paper interleaves test and repair analysis and supports an exact solution without failure bitmap. The basic search procedure is combined with an efficient technique to continuously reduce the problem complexity and keep the test and analysis time low.

Embedded memories are part of almost any embedded system. To ensure an error free operation, error detecting/correcting codes or alternative schemes for on-line consistency checking can be used. The trade-offs with respect to error detection capabilities and hardware cost has been investigated in previous work. However, very often embedded systems also have to work with small batteries (e.g. mobile devices), and power consumption becomes a second crucial issue. In this paper a low power design for on-line consistency checking is proposed. The proposed scheme is analyzed with respect to its power consumption and compared to error detecting/correcting schemes based on error correcting codes. The results show that on-line consistency checking based on the modulo-2 address characteristic can ensure both low error detection latencies and reduced power consumption in contrast to alternative schemes.

Reducing test application time and test data volume are major challenges in SoC design. In the case of IP cores, where no structural information is available, a common strategy is to compress the test data T/sub D/ provided by the core vendor into an encoded format T/sub E/. Only the smaller set T/sub E/ is stored on the ATE, and during test the original test data T/sub D/ are regenerated by an on-chip decompressor. However, most of the encoding schemes suffer from two major drawbacks: Firstly, the irregularity of the encoded test data requires a complex test control including a handshake between the ATE and the system under test. Secondly, compression and decompression is very efficient for circuits with a single scan chain, however the extension to multiple scan chains requires either a separate decompressor for each chain or a serialization of the test data. So far, only a few approaches have been proposed trying to overcome these problems. Instead of dealing with the test vectors these approaches work with the slices to be fed into the scan chains, but they still allow a considerable degree of irregularity in the test application process. We propose a new dictionary based compression scheme which allows a fully regular test application while keeping the storage requirements low. Due to the regularity of the scheme the advantages of a multiple-scan architecture are preserved, and very low test times can be achieved.

Store-and-generate techniques encode a given test set and regenerate the original test set during the test with the help of a decoder. Previous research has shown that runlength coding, particularly alternating run-length coding, can provide high compression ratios for the test data. However, experimental data show that longer run-lengths are distributed sparsely in the code space and often occur only once, which implies an inefficient encoding. In this study a hybrid encoding strategy is presented which overcomes this problem by combining both the advantages of run-length and dictionary-based encoding. The compression ratios strongly depend on the strategy of mapping don't cares in the original test set to zeros or ones. To find the best assignment an algorithm is proposed which minimizes the total size of the test data consisting of the encoded test set and the dictionary. Experimental results show that the proposed approach works particularly well for larger examples yielding a significant reduction of the total test data storage compared to pure alternating runlength coding.

This paper presents an integrated approach for both built-in online and off-line testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during off-line test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection. Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

A novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility.

In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical approaches for test width compression and with pseudorandom pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters.

The paper introduces the new concept of symmetric transparent BIST for RAMs. This concept allows one to skip the signature prediction phase of conventional transparent BIST approaches and therefore yields a significant reduction of test time. The hardware cost and the fault coverage of the new scheme remain comparable to that of a traditional transparent BIST scheme. In many cases, experimental studies even show a higher fault coverage obtained in shorter test time.

This paper presents a new technique for on-line consistency checking of embedded DRAMs. The basic idea is to use the periodic refresh operation for concurrently computing a test characteristic of the memory contents and compare it to a precomputed reference characteristic. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). It also achieves a very high error coverage at low hardware costs. Therefore it perfectly complements standard on-line checking approaches relying on error detecting codes, where the detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.

After write operations, BIST schemes for RAMs relying on signature analysis must compress the entire memory contents to update the reference signature. This paper introduces a new scheme for output data compression which avoids this overhead while retaining the benefits of signature analysis. The proposed technique is based on a new memory characteristic derived as the module-2 sum of all addresses pointing to non-zero cells. This characteristic can be adjusted concurrently with write operations by simple EXOR-operations on the initial characteristic and on the addresses affected by the change.

A fast fault-tolerant controller structure is presented which is capable of recovering from transient faults by performing a rollback operation in hardware. The proposed fault-tolerant controller structure utilizes the rollback hardware also for system mode and this way achieves performance improvements of more than 50% compared to controller structures made fault tolerant by conventional techniques, while the hardware overhead is often negligible. The proposed approach is compatible with state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.

This paper presents a new scan-based BIST schemewhich achieves very high fault coverage without the deficienciesof previously proposed schemes. This approach utilizes scan orderand polarity in scan synthesis, effectively converting the scanchain into a ROM capable of storing some "center" patterns fromwhich the other vectors are derived by randomly complementingsome of their coordinates. Experimental results demonstrate that avery high fault coverage can be obtained without any modificationof the mission logic, no test data to store and very simple BISThardware which does not depend on the size of the circuit.

In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements. In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware.

Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set. Furthermore, it is demonstrated that the proposed approach of combining ATPG and BIST synthesis leads to a considerably reduced hardware overhead compared to encoding a conventionally generated test set.

We propose a new scheme for built-in test (BIT) that uses multiple-polynomial linear feedback shift registers (MP-LFSR's). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSR's produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSR's. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with s specified bits in an s-stage LFSR with 16 polynomials is 1-10/sup -6/. We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paper also shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage.>

The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for rest purposes. This leads to some serious drawbacks concerning the fault coverage, the system speed and the area overhead. A synthesis technique is presented which uses the additional test register also to implement the system function by supporting self-testable pipeline-like controller structures. It will be shown, that if the need of two different registers in the final structure is already taken into account during synthesis, then the overall number of flipflops can be reduced, and the fault coverage and system speed call be enhanced. The presented algorithm constructs realizations of a given finite state machine a self-testable structure. The efficiency of the procedure is ensured by a very precise characterization of the space of suitable realizations, which avoids the computational overhead of previously published algorithms.

The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the test strategy requires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the well-known benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation.>

Over the past years special chips for external tests have been successfully used for random pattern testing. The authors present a technique for combining the advantages of such a low-cost test with the advantages of pseudoexhaustive testing, which are enhanced fault coverage and simplified test pattern generation. To achieve this goal, two tasks are accomplished. First, an algorithm is developed for pseudoexhaustive test pattern generation, which ensures a feasible test length. Second, a chip design for applying these test patterns to a device under test is presented. The chip is programmed by the output of the proposed algorithm and controls the entire test. The technique is first applied to devices with a scan path and then extended to sequential circuits. A large number of benchmark circuits have been investigated, and the results are presented.>

The concept of a pseudoexhaustive test for sequential circuits is introduced. Instead of test sets one applies pseudoexhaustive test sequences of a limited length, which provides well-known benefits as far as fault coverage, self-test capability, and simplicity of test generation are concerned. Some flip flops and latches are integrated into an incomplete scan path, such that each possible state of the circuit is reachable within a few steps. Some more flip flops and some new segmentation cells are added to the partial scan path in order to make a pseudoexhaustive test feasible. Algorithms for placing these devices automatically are presented. Also it is shown how to transform a pseudoexhaustive test set into a pseudoexhaustive test sequence of a similar size. The analyzed examples show that a conventional complete scan path without additional testability features requires more hardware overhead than the proposed test strategy, which retains all the known benefits of a pseudoexhaustive test.>