This paper addresses the problem of state assignment for large Finite State Machines (FSM).This is an important problem in the high performance digital system design where added functionality often comes at the expense of a larger (and slower) FSM to control the system.We present a new method to solve the graph embedding problem which is the main step in the state assignment process.The basic idea is to place the state adjacency graph in a two-dimensional grid while minimizing the total wire length.The grid is then mapped into an n-dimensional hypercube while nearly preserving the adjacency relations that is with dilation at most 2. Experimental results are presented and compared with those of NOVA.

This paper addresses the problem of partitioning a large PLA into a number of smaller PLA's (sub-PLA's) such that the total area of these sub-PLA's is minimum and the cycle time of the partitioned circuit is minimized. First, we describe an iterative improvement method that deals with the case that sub-PLA's assume arbitrary sizes. Second, we present a partitioning technique based on fuzzy logic that deals with the case that the sizes of the sub-PLA's are fixed. Finally, we describe a method that considers not only delay through each sub-PLA, but also loading of sub-PLA's on the stage that is driving them. These techniques have been implemented and significantly outperformed conventional PLA partitioning schemes.