Post-Quantum Cryptography (PQC) schemes, such as Learning with Errors (LWE), rely on adding Gaussian noise to arithmetic operations to achieve security against quantum adversaries. Efficient generation of this noise is critical for hardware implementations, particularly in resource-constrained environments like IoT devices. Traditional approaches employ Gaussian samplers to produce discrete Gaussian noise, but these methods introduce significant area overhead and latency, limiting their practical applicability. In this work, we propose a novel hardware architecture that generates Gaussian-like noise using controlled XOR-based bit-flip operations integrated directly into arithmetic circuits. Our approach achieves up to a$3 \times$reduction in area compared to conventional hardware Gaussian samplers, while introducing negligible delay. The resulting architectures provide an efficient and lightweight solution for noise injection, making them highly suitable for deployment in constrained hardware platforms.

International audience

Physical Unclonable Functions (PUFs) play a crucial role in enhancing the security of electronic devices by leveraging inherent manufacturing variations to generate unique and unclonable identifiers. This study explores the vulnerability of Ring Oscillator-based PUFs (RO-PUFs) to thermal attacks, focusing on two semiconductor technologies: Bulk 65 nm and Fully Depleted Silicon on Insulator (FDSOI) in 28 nm. Through detailed simulations, the effects of uniform and localized thermal variations on the stability of ring oscillator frequencies are analyzed. The results reveal that while the Bulk 65 nm technology shows resistance to uniform thermal attacks, it is highly sensitive to localized attacks. In contrast, the FDSOI 28 nm technology is vulnerable to both types of attacks due to its low variability. These observations underscore the need for robust countermeasures in the design of PUFs to ensure their reliability under varying thermal conditions.

Physical unclonable functions (PUFs) leverage process variability to generate unique signatures in electronic devices. They are a strong alternative to conventional security mechanisms as they do not rely on non-volatile memories (NVMs) to store the secrets. However, PUFs can be influenced by external factors and may exhibit biased output distributions, leading to vulnerabilities that could compromise their uniqueness and resistance to cloning. The quality of a PUF is evaluated through a common set of metrics such as uniformity, bit-aliasing, uniqueness, and reliability. However, the lack of standardized methodologies hinders effective comparisons between diverse PUF designs, limiting the broader understanding of their performance. Besides, the underlying physics and mechanisms of PUFs makes them difficult to study and mitigate potential vulnerabilities and attacks. Overall, the quality metrics for PUFs are still evolving, and there is ongoing research to address these challenges and develop more robust and reliable PUFs. In this article, we demonstrate the limitations of current PUF evaluation metrics using experimental data and introduce a novel set of metrics that provide a more rigorous and comprehensive assessment.

Memristive devices are widely explored as artificial synapses for hardware neuromorphic computing, offering analog programmability and in-memory learning capabilities. However, their limited endurance remains a critical concern for online training applications. In this work, we analyze the evolution of synaptic weights during spike-timing-dependent plasticity (STDP)based learning in a spiking neural network (SNN), to track weight updates and infer spike-timing dynamics during training. Our results show that synaptic activity is sparse and concentrated in a subset of connections, with many synapses remaining inactive throughout training. Moreover, even the most active synapses undergo relatively few significant updates, suggesting that the effective endurance stress is much lower than that assumed in conventional full-range cycling tests. We further propose that inferred timing differences can serve as a proxy for estimating precise electrical stress during training, enabling more accurate memristive endurance assessment during training. These findings support the feasibility of online learning with endurance-limited devices and offer insights for optimizing reliability in neuromorphic hardware.

Physical Unclonable Functions (PUFs) have emerged in recent years as a reliable alternative to non-volatile memory for cryptographic applications. Their main advantage lies in the fact that they do not store data within the chip but generate unique responses on demand. However, some responses may be unreliable over time due to small variations in temperature or voltage, whether under normal operating conditions or during attacks, such as thermal attacks. This paper presents a novel filtering technique that has been applied to a ring oscillator PUF (RO-PUF) implemented on an FPGA, designed to address the issue of unreliable and biased responses.

Physical Unclonable Functions (PUFs) present a promising alternative to traditional cryptographic techniques for securing sensitive information in modern circuits. By exploiting inherent process variability, PUFs generate unique secrets dynamically, thus eliminating the need for data storage. However, a major challenge in PUF-based security is distinguishing valid PUFs from those that may have been tampered with or are invalid (i.e., not belonging to the original design). This paper proposes a data mining-based approach for detecting anomalies and identifying tampered or invalid PUFs. The proposed method mines a set of rules that describe the expected behavior of the PUF, with deviations from these rules signaling potential security issues and vulnerabilities. Experimental results demonstrate that the method effectively identifies invalid or tampered PUFs, showcasing its potential for enhancing PUF-based security systems.

Physical Unclonable Functions (PUFs) offer a promising alternative to conventional cryptographic techniques to secure sensitive information in modern circuits. PUFs leverage inherent process variability to dynamically generate unique secrets, eliminating the need for data storage. However, a significant challenge in PUF-based security is differentiating between valid PUFs and those that may have been tampered with or are invalid (i.e., not belonging to the original design). This paper presents an innovative data mining-based technique for detecting anomalies and identifying tampered or invalid PUFs. The proposed method extracts a set of rules that describe the expected behavior of the PUF, where deviations from these rules indicate potential security issues and vulnerabilities. Experimental results demonstrate that the method effectively detects invalid or tampered PUFs, highlighting its potential to strengthen PUF-based security systems.

International audience

Physical Unclonable Functions (PUFs) provide a promising security mechanism by leveraging inherent process variations to generate unique, hardware-bound secrets without requiring secure storage. However, ensuring PUF reliability and detecting potential tampering remain critical challenges. This paper presents a fuzzy logic-based classification system that determines the authenticity of PUF responses using three key metrics: Reliability, Stability, and Reliability Invariance. The system classifies PUF responses into three categories: Trustable, Tampered, and Undecided. This approach enhances the automatic detection of unreliable responses that may indicate tampering while ensuring the fidelity of PUF responses over time. By applying fuzzy inference rules, our method achieves high accuracy in distinguishing between trustworthy and compromised PUFs. Experimental results demonstrate the effectiveness of our approach, making it a valuable method and tool for hardware security applications.

In the contemporary security landscape, the incorporation of photonics has emerged as a transformative force, unlocking a spectrum of possibilities to enhance the resilience and effectiveness of security primitives. This integration represents more than a mere technological augmentation; it signifies a paradigm shift towards innovative approaches capable of delivering security primitives with key properties for low-power systems. This not only augments the robustness of security frameworks, but also paves the way for novel strategies that adapt to the evolving challenges of the digital age. This paper discusses the security layers and related services that will be developed, modeled, and evaluated within the Horizon Europe NEUROPULS project. These layers will exploit novel implementations for security primitives based on physical un-clonable functions (PUFs) using integrated photonics technology. Their objective is to provide a series of services to support the secure operation of a neuromorphic photonic accelerator for edge comnuting applications.

Security primitives such as Physical Unclonable Functions (PUFs) or True Random Number Generators (TRNGs), have emerged as hardware roots of trust for ensuring the security of modern applications. However, these primitives display susceptibility to physical attacks, among them, in the face of temperature variations. Previous research has established the feasibility of attacks exploiting temperature fluctuations to compromise the security of these primitives. Specifically, when implemented on FPGAs, programmable components can be vulnerable to alterations induced by thermal changes. These findings underscore the need to deepen the understanding of the implications of temperature sensitivity on the security and robustness of these security mechanisms. This paper studies how heat affects, both instantaneously and permanently, the working of ring oscillators, which are the building blocks of PUFs based on Ring Oscillators. The study also suggests how to exploit these effects to bias the PUf responses, enabling thus the possibility of its cloning.

This paper presents GemIMC, a High Level Synthesis (HLS) based configurable digital unit architecture for accelerating Neural Networks (NN) at the edge using In Memory Computing (IMC). The proposed architecture is capable of supporting any type of memory technology, be it CMOS or resitive, with digital or analog storage capabilities. GemIMC aims to facilitate design space exploration among different IMC-related parameters and provide a top architecture for prototyping. By taking as input the IMC-tile parameters such as storage type (analog/digital), size, latency, power and process variability, GemIMC provides a an estimation of the full system's latency, area, and power consumption, taking into account the full digital control. The Tensorfiow-to-GemIMC environment flow allows for direct evaluation of the ineference accuracy for any type of NN, considering the variability associated with analog computation (when needed). The proposed work provides a flexible and efficient solution for IMC-based NN inference on the edge, along with a methodology for writing the IMC tile model to ensure compatibility with the top architecture.

The need to achieve statistically relevant results in electrical simulations requires a large number of iterations under different operating conditions. Moreover, the nature of parametric simulations makes the collection and filtering of the results non-trivial. To tackle these issues, scripts are normally used to control all the parameters. Still, this approach is usually ad-hoc and platform dependent, making the whole procedure hardly reusable, scalable and versatile. We propose a generic, open-source framework to generate complex stimuli and parameters for electrical simulations, together with a programmable Spice- and Verilog-A-based module capable of observing and logging internal states of the circuit to facilitate further result analysis.

This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases.

PUFs (Physical Unclonable Functions) have been proposed as a cost-effective solution to provide a root of trust for electronic devices which exploit intrinsic process variability. They generate identification signatures and keys only when the devices are turned on, avoiding the storage of sensitive information in memories that could be targeted by attacks. Although PUFs have many perceived advantages, they also have disadvantages such as sensitivity to temperature. Indeed their behaviour can be affected by the fact that high temperatures can accelerate permanent and transient phenomena, such as aging and transistor switching speed. In this paper we show the effects of externally induced heat on the functioning of Ring Oscillators (ROs), which form the basis of RO-PUFs. Moreover, we discuss the feasibility of temperature attacks on PUFs.

Embedded systems are vulnerable to significant security threats from Fault Injection Attacks (FIAs), which allow attackers to gain access to confidential information. While various attack detectors have been proposed in the literature to detect different types of FIAs, these detectors themselves are susceptible to such attacks and can be compromised. Hence, the robustness of these detectors is critical in maintaining the security of embedded systems. The focus of this study is to evaluate the robustness of digital circuits and delay-based digital detectors against a new type of FIA called Power-Off Attack (POA). POA occurs when the power to the chip is turned off, and the detectors are not active. Following a POA attack, the circuit or its detectors may not function properly when the power is turned back on, which can allow other attacks to be applied without being detected if the detectors are less sensitive. This study implements two detectors on Xilinx Artix-7 FPGAs and examines the impact of heating cycles on detector characteristics when the FPGA is in various states, including power-off, power-on, and inactive states (such as clock-freezing mode). Our experiments reveal that heating cycles in power-off mode can alter the FPGA component delays and the accuracy of its detectors, which highlights the vulnerability of these systems to POA and potential issues for embedded system security.

Physical Unclonable Functions (PUFs) allow generating an intrinsic signature in electronic device thanks to process variability. One of the most researched solutions for PUF implementation is the Ring Oscillator PUF (RO-PUF). This solution is based on the comparison of the frequency of 2 identically designed ROs in an IC. Ideally these 2 ROs would have the same frequency, however this in not the case in reality due to fabrication-induced process variability. By measuring and comparing their actual frequency, a 1-bit PUF response is generated. The RO-PUF has been demonstrated to satisfy the principal randomness requirements (uniformity and uniqueness) but it suffers from problems such as bitaliasing and unrepeatability (i.e. low reliability). In this paper we perform a thorough analysis of RO-PUF bitaliasing and reliability and propose a methodology for its analytical estimation based on the variability profile of the underling technology.

The field of neuromorphic computing has been rapidly evolving in recent years, with an increasing focus on hardware design and reliability. This special session paper provides an overview of the recent developments in neuromorphic computing, focusing on hardware design and reliability. We first review the traditional CMOS-based approaches to neuromorphic hardware design and identify the challenges related to scalability, latency, and power consumption. We then investigate alternative approaches based on emerging technologies, specifically integrated photonics approaches within the NEUROPULS project. Finally, we examine the impact of device variability and aging on the reliability of neuromorphic hardware and present techniques for mitigating these effects. This review is intended to serve as a valuable resource for researchers and practitioners in neuromorphic computing.

Today we observe amazing performance achieved by Machine Learning (ML); for specific tasks it even surpasses human capabilities. Unfortunately, nothing comes for free: the hidden cost behind ML performance stems from its high complexity in terms of operations to be computed and the involved amount of data. For this reasons, custom Artificial Intelligence hardware accelerators based on alternative computing paradigms are attracting large interest. Such dedicated devices support the energy-hungry data movement, speed of computation, and memory resources that MLs require to realize their full potential. However, when ML is deployed on safety-/mission-critical applications, dependability becomes a concern. This paper presents the state of the art of custom Artificial Intelligence hardware architectures for ML, here Spiking and Convolutional Neural Networks, and shows the best practices to evaluate their dependability.

Spiking neural networks (SNN) are biologically plausible networks. Compared to formal neural networks, they come with huge benefits related to their asynchronous processing and massively parallel architecture. Recent developments in neuromorphics aim to implement these SNNs in hardware to fully exploit their potential in terms of low energy consumption. In this paper, the plasticity of a multi-state conductance synapse in SNN is shown. The synapse is a compound of multiple Magnetic Tunnel Junction (MTJ) devices connected in parallel. The network performs learning by potentiation and depression of the synapses. In this paper we show how these two mechanisms can be obtained in hardware-implemented SNNs. We present a methodology to achieve the Spike Timing Dependent Plasticity (STDP) learning rule in hardware by carefully engineering the post- and pre-synaptic signals. We demonstrate synaptic plasticity as a function of the relative spiking time of input and output neurons only.

In this paper we propose an on-line test methodology for RO-PUF reliability which enables high accuracy in the results since it is not based on predictive simplified models of the device variability and noise, but on actual technological electrical models and high versatility since it is not based on measurements extracted from a single technology.

International audience

Hardware device identification has become an important feature for enhancing the security and the trust of interconnected objects. In this paper, we present a device identification method based on measuring physical and electrical properties of the device, while controlling its switching activity. The method is general an applicable to a large range of devices from FPGAs to processors, as long as they embed sensors (such as temperature and voltage) and their measurements are available. The method is enabled by the fact that both the sensors and the effects of the switching activity on the circuit are uniquely affected by manufacturing-induced process variability. The device identification based on this method is made possible by the use of machine learning. The efficiency of the method has been evaluated by a preliminary study conducted on eleven FPGAs.

Machine learning techniques have significantly changed our lives. They helped improving our everyday routines, but they also demonstrated to be an extremely helpful tool for more advanced and complex applications. However, the implications of hardware security problems under a massive diffusion of machine learning techniques are still to be completely understood. This paper first highlights novel applications of machine learning for hardware security, such as evaluation of post quantum cryptography hardware and extraction of physically unclonable functions from neural networks. Later, practical model extraction attack based on electromagnetic side-channel measurements are demonstrated followed by a discussion of strategies to protect proprietary models by watermarking them.

In this paper we present a novel hidden-delay-fault sensor design and a preliminary analysis of its circuit integration and applicability. In our proposed method, the delay sensing is achieved by sampling data on both rising and falling clock edges and using a variable duty cycle to control the length of the path to be tested. The main advantage of our proposed method is that it works at nominal frequency, it can detect hidden-delay-faults on short paths and it is versatile in its applicability. It can be used (i) during testing to perform user-defined hidden-delay-fault test, (ii) for reliability degradation estimation due to process, environmental variations and ageing, and (iii) in security to detect the insertion of Trojan horses that alter the path delay.

Physically Unclonable Functions (PUFs) are cryptographic primitives used to implement low-cost device authentication and secure secret key generation. Weak PUFs (i.e., devices able to generate a single signature or to deal with a limited number of challenges) and Strong PUFs (i.e., devices able to deal with large number of challenges) are widely discussed in literature. Strong PUFs are susceptible to machine learning and modeling attacks. In this paper we propose a solution where the challenges of a Strong PUF are encrypted in order to remove the linear challenge-response correlation that can be exploited by those attacks. In this context, a ZeroBit Error Rate Weak PUF generates the encryption key so that all PUF instances have a different, nonlinear correlation between respective challenges and responses. We present two implementations of the proposed solution, and we demonstrate their resilience against machine learning attacks.

This paper is dedicated to the IEEE European Test Symposium (ETS). It offers an overview of all the European Test Workshop and Symposium events, from its first edition in 1996 to the next edition in 2020.

The research work presented in this paper deals with the fault analysis in hardware-implemented Spiking Neural Networks with special emphasis on circuits designed to perform unsupervised, on-line learning. The paper describes the benefits of such neuromorphic systems, the possibilities of their hardware integration, but more importantly, it underlines the main concerns related to their resilience face to different types of faults. An overview of pertinent fault models and a methodology for conducting fault injection campaigns is described and different scenarios of faulty behaviors occurring after/before the STDP learning are shown.

Hardware true random number generators (TRNGs) yield random numbers from physical processes. Traditionally, such devices are based on statistically random events such as thermal noise or other quantum phenomena. In this brief, we propose a novel TRNG design using a spin-transfer torque magnetic tunnel junction (MTJ) device. Our solution exploits the stochastic nature of the MTJ switching, and the behavior of an XOR gate dealing with probabilistic signals. We show that by using multiple MTJ devices, the proposed TRNG succeeds in filtering the negative effect of environmental changes as well as fabrication-induced variability and generates random sequences with high-entropy under any conditions.

The emergence of non-volatile random access memory technologies, such as resistive and spintronic RAMs are triggering intense interdisciplinary activity. These technologies have the potential of providing many benefits, such as energy efficiency, high integration density, CMOS-compatibility, re-configurability, non-volatility and open the path towards novel computational structures and approaches, for the traditional Von-Neumann architectures and beyond. These promising characteristics, coupled with the ever-increasing limitations faced by traditional CMOS-based storage and computational structures, have driven the research community towards completely revisiting the existing computing and storage paradigms, now focusing on providing hardware solutions for in-memory and neuromorphic computing. This has resulted in an intensified research activity in the device physics, striving to achieve circuit-worth devices, reliable compact models and novel architectures. The purpose of this paper is to provide a comprehensive overview of the device physics, issues related to its use in electronic circuits, methodologies for their compact modelling and simulations, and their integration in storage and computational structures.

This paper provides an overview of the challenges faced by hardware implemented Spiking Neural Networks, from device to circuit design, reliability and test. We present a comprehensive description of the state-of-the-art neuromorphic architectures inspired by brain computation, with special emphasis on Spiking Neural Networks (SNNs), together with emerging technologies that have enabled such systems, namely Phase Change and Metal Oxide Resistive Memories. Finally, we discuss the main challenges faced by hardware implementations of SNNs, their reliability and post-fabrication test issues.

In this paper we propose a methodology for reliability evaluation, failure prediction, and failure mitigation of a STT-MRAM memory under different supply voltage conditions (i.e., DVS scenarios). The methodology is based on the design of read/write failure predictor registers which are able to predict the memory failure probability for a given DVS scenario. The predicted results are used to re-tune the supply voltage such that the memory reliability is assured.

The power and reliability issues of today's memories limit the improvements attained by their implementation in scaled technology nodes. Several emergent memory technologies attempt to address the technical constraints of today's memories, amongst which, one of the most promising solutions is the Spin-Transfer-Torque Magnetic Random Access Memories (STT-MRAMs). One of the great advantages of the emerging memories is that they favor increasing system complexity and performance. New applications and computation paradigms, such as neuromorphic computing, unfeasible a few years back due to technological limitations, can take profit from this technology. Intensive research has been conducted recently related to magnetic device physics and its implementation as dedicated hardware for neuromorphic computing, however, little work has been conducted to evaluate the reliability of such circuits. In this paper we investigate the effect of meaningful MTJ reliability issues on the behavior of an MTJ-based Spiking Neural Network.

A hardware True Random Number Generator (TRNG) yields random numbers from a physical process. Traditionally, such devices are based on statistically random signals such as thermal noise or other quantum phenomena. In this paper we propose an innovative TRNG design using a Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) device. We exploit the stochastic nature of the MTJ device switching, and perform on-the-fly temperature/current variation compensation. We show that the proposed solution keeps up with environmental changes and generates random sequences with high probability.

The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Inner properties of STT-MRAMs make them suitable for the implementation of basic security primitives such Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs). PUFs are emerging primitives used to implement low-cost device authentication and secure secret key generation. On the other hand, TRNGs generate random numbers from a physical process. We will show how it is possible to exploit (i) the high variability affecting the electrical resistance of the magnetic device to build a robust, unclonable and unpredictable PUF, and (ii) the stochastic nature of the write operation in the magnetic device to generate randomly distributed numbers.

Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to implement low-cost device authentication and secure secret key generation. Weak PUF s (i.e., devices able to generate a single signature or to deal with a limited number of challenges) are widely discussed in literature. One of the most investigated solutions today is based on SRAMs. However, the rapid development of low-power, high-density, high-performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. In this article, we propose an innovative PUF design based on STT-MRAM memory. We exploit the high variability affecting the electrical resistance of the Magnetic Tunnel Junction (MTJ) device in anti-parallel magnetization. We will demonstrate that the proposed solution is robust, unclonable, and unpredictable.

One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. In this paper, we estimate the STT-MRAM cell reliability under fabrication- and aging-induced process variability, by evaluating its failure probability. We analyze the effect of control voltage tuning on the fresh and aged cell failure probabilities and, as a result, we propose a power- and aging-aware circuit level variability mitigation technique based on control voltage tuning. We observed that increasing the values of control voltages, the cell failure probability is reduced at different extends (according to the control voltage under variation), but also that the power consumption is increased. As a result, we have identified the control voltage with the highest impact on the fresh cell reliability, and on the endurance of the cell under study. Subsequently, by performing a power/reliability trade-off analysis, the appropriate value of this control voltage is determined.

Due to the rapid development of smartphones, notebooks and tablets, the need for high density, low power, high performance SoCs has pushed the well-established embedded memory technologies to their limits. To overcome the existing memory issues, emerging memory technologies are being developed and implemented. The focus is placed on non-volatile technologies., which should meet the high demands of tomorrow applications. The emerging technologies are expected to integrate the best features of SRAMs, DRAMs, and Flash memories at the same time. That includes high performance and high density similar to SRAMs and DRAMs respectively, non-volatility, good endurance features, good integration, low power profile, resistance to radiation effects, and ability to scale below 20 nm. The emerging memory technologies being studied today are the magnetic type RAM, the resistive type RAM and the Phase-change RAM. However, since these are new technologies., their modeling is still controversial and their shortcomings not completely cha-racterized. In the paper we present a methodology for memory reliability estimation when process variability and aging phenomena are accounted for at physical level. The method relies on a highly parameterized physical description of emerging memory technologies, based on which, a complete characterization of the memory technology is performed, and the resulting issues of the fabricated cell identified.

SRAM testing is becoming more and more challenging due to issues caused by continuous device scaling. Fabricated SRAMs are submitted to random and systematic process variability, which strongly affect the cell's behavior and also the ability of test algorithms to detect faults. Traditionally, bias conditions have been used to improve the behavior of the SRAM under process variations by applying body bias to compensate for the effect of variability. Based on the same principle, bias conditions also affect the cell's behavior when resistive-opens are present, hence affecting test's defect coverage capability. Both body- and source-bias conditions are analyzed in this paper to find the way to improve defect detect ability in the SRAM cell. Source-biasing has been proven to be the more effective of the two, leading to more than 3X improvement of the defect detected value. Also, by adapting the source-bias conditions to process parameter values, over- and under-testing of the SRAM can be avoided.

Functional operations of a Static Random Access Memory (SRAM) are strongly affected by random variability in core-cell transistors and by the variability-induced threshold voltage mismatch between the transistors of the Input-Output (IO) circuitry (especially Sense Amplifiers). This variability also affects the faulty behavior of the SRAM array. This paper is focused on the analysis of static and dynamic faults due to resistive-open defects in the SRAM core-cell, taking into account the effects of random process variability in core-cells and IO circuitry. Statistical analyses have been performed to evaluate the SRAM failure probabilities accounting for defects at each possible location. The results show that random process variability in the SRAM core-cell and IO circuitry have an important effect on the behavior of an SRAM array and also on the defect coverage of various commonly-used test sequences. It is shown that under variability, the minimum defect size detected with maximum probability is more than 2X larger than the minimum size detected in nominal conditions, thus leaving a large range of defects undetected. Several stress conditions during test have been evaluated to assess their capability to increase the defect coverage under random process variability.

In current technologies, the robustness of Static Random Access Memories (SRAM) has to be investigated under any possible source of disturbance. In this paper, we evaluate the reliability of an SRAM cell exposed to atmospheric neutron radiation, affected by random threshold voltage variation and under different operation conditions (supply voltage, process corner and temperature). The SRAM cell's Soft Error Rate (SER) at simulation level is estimated using accurate models of atmospheric neutron induced currents. The study shows that in extreme operation conditions and under random process variability, the SER of an SRAM can reach values up to 3X larger than the nominal value, or down to 2X smaller than the nominal value. This large SER range confirms the importance of our study and justifies the need for further evaluation of circuits under radiation at the simulation level.

The efficiency of different assist techniques for SRAM cell functionality improvement under the influence of random process variation is studied in this paper. The sensitivity of an SRAM cell functionality metrics when using control voltage level assist techniques is analyzed in read and write operation modes. The efficiency of the assist techniques is estimated by means of parametric analysis. The purpose is to find the degree of functionality metric improvement in each operation mode. The Acceptance Region concept is used for parametric analysis of SRAM cell functionality under random threshold voltage variations. In order to increase the reliability of the SRAM several assist techniques, chosen among the most efficient ones for each operation mode, are considered. This analysis offers a qualitative indication of the cell's functionality improvement by means of the efficient computation of a metric in parameter domain analysis. The results are proven to have high correlation with the ones obtained by means of the classical Monte Carlo simulations with significant savings in comparing different assist techniques.

Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM)defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise.

Process variability is becoming a major challenge in CMOS design of general and embedded SRAMs in particular due to continuous device scaling. The main problems are the increased static power and reduced operating margins, robustness and reliability. A common way to reduce the static power consumption of an SRAM memory array is to decrease its supply voltage when in memory retention mode. However, this leads to a further reduction in memory robustness. The most common tool for statistical analysis of circuits under process variability is standard Monte Carlo simulation which has been proven to be too expensive when applied on an ultra dense SRAM. In this paper a statistical robustness analysis method is proposed based on decoupling statistical integration from robustness region determination in the parameter domain. The robustness is estimated with a ~ 556X speed up relation to Monte Carlo and an error of ~ 1%.

One of the main issues in scaled SRAMs is the increase in static power. A common way to reduce the static power consumption of an SRAM array is to decrease its supply voltage when in memory retention mode. Decreasing the supply voltage however has a strong negative effect on the stability of the SRAM cell. This paper statistically analyzes the behavior of the 6T SRAM cell in data retention mode, under process variability. The failure probabilities under various supply voltages are determined for different technology nodes, and the Data Retention Voltage is determined. For the 45nm PTM SRAM cell under random threshold voltage variation, the Data Retention Voltage is found to be 423mV while for the 16nm PTM SRAM, the DRV is 649mV.

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to user's requirements.

Increased die-to-die and on-die variations in scaled technologies can lead to parametric failures (Read/Write/Access) in embedded SRAMs. Conventionally, SRAM bit-cell failure analysis is based on the Static Noise Margin (SNM), a metric that leads to conservative estimate of design yield. In this paper we present a method of dynamic noise margin (DNM) estimation based on the modeling technique developed that can efficiently estimate failures in bit-cells under parameter variations. The proposed DNM estimation method is fast, and can accurately estimate the SRAM yield. Monte Carlo simulation results show that the proposed DNM closely matches the results from SPICE analysis.